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cy8c20xx6a/s 1.8 v programmable capsense ? controller with smartsense? auto-tuning 1?33 buttons, 0?6 sliders cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-54459 rev. *v revised january 13, 2015 1.8 v programmable capsense ? controller with smartsense? auto-tuning 1?33 buttons, 0?6 sliders features low power capsense ? block with smartsense auto-tuning ? patented csa_emc, cs d sensing algorithms ? smartsense_emc auto-tuning ? sets and maintains optimal sensor performance during run time ? eliminates system tuning during devel opment and production ? compensates for variations in manufacturing process low average power consumption ? 28 a/sensor in run time (wake-up and scan once every 125 ms) powerful harvard-architecture processor ? m8c cpu with a max speed of 24 mhz operating range: 1.71 v to 5.5 v ? standby mode 1.1 a (typ) ? deep sleep 0.1 a (typ) operating temperature range: ?40 c to +85 c flexible on-chip memory ? 8 kb flash, 1 kb sram ? 16 kb flash, 2 kb sram ? 32 kb flash, 2 kb sram ? read while write with eeprom emulation ? 50,000 flash erase/write cycles ? in-system programming simplif ies manufacturing process four clock sources ? internal main oscillato r (imo): 6/12/24 mhz ? internal low-speed oscillator (ilo) at 32 khz for watchdog and sleep timers ? external 32 khz crystal oscillator ? external clock input programmable pin configurations ? up to 36 general-purpose i/os (gpios) configurable as buttons or sliders ? dual mode gpio (analog inputs and digital i/o supported) ? high sink current of 25 ma per gpio ? max sink current 120 ma for all gpios ? source current ? 5 ma on ports 0 and 1 ? 1 ma on ports 2,3 and 4 ? configurable internal pull-up, high-z and open drain modes ? selectable, regulated digital i/o on port 1 ? configurable input threshold on port 1 versatile analog functions ? internal analog bus supports connection of multiple sensors to form ganged proximity sensor ? internal low-dropout voltage regulator for high power supply rejection ratio (psrr) full-speed usb ? 12 mbps usb 2.0 compliant additional system resources ? i2c slave: ? selectable to 50 khz, 100 khz, or 400 khz ? configurable up to 12 mhz spi master and slave ? three 16-bit timers ? watchdog and sleep timers ? integrated supervisory circuit ? 10-bit incremental analog-to-digital converter (adc) with internal voltage reference ? two general-purpose high speed, low power analog comparators complete development tools ? free development tool (psoc designer?) sensor and package options ? 10 sensors ? qfn 16, 24 ? 16 sensors ? qfn 24 ? 22 / 25 sensors ? qfn 32 ? 24 sensors - wlcsp 30 ? 31 sensors ? ssop 48 ? 33 sensors ? qfn 48 errata: for information on silicon errata, see ?errata? on page 46. details include trigger conditions, devices affected, and proposed workaround
cy8c20xx6a/s document number: 001-54459 rev. *v page 2 of 52 logic block diagram capsense system 1k/2k sram interrupt controller sleep and watchdog multiple clock sources internal low speed oscillator (ilo) 6/12/24 mhz internal main oscillator (imo) psoc core cpu core (m8c) supervisory rom (srom) 8k/16k/32k flash nonvolatile memory system resources system bus analog reference system bus port 3 port 2 port 1 port 0 capsense module global analog interconnect 1.8/2.5/3v ldo analog mux two comparators i2c slave spi master/ slave por and lvd usb system resets internal voltage references three 16-bit programmable timers pwrsys (regulator) port 4 digital clocks [1] note 1. internal voltage regulator for internal circuitry
cy8c20xx6a/s document number: 001-54459 rev. *v page 3 of 52 more information cypress provides a wealth of data at www.cypress.com to help you to select the right psoc device for your design, and to help you to quickly and effectively integrate the device into your design. for a comprehensive list of resources, see the knowledge base article kba92181, resources available for capsense? controllers . following is an abbreviated list for capsense devices: overview: capsense portfolio , capsense roadmap product selectors: capsense , capsense plus , capsense express , psoc3 with capsense , psoc5 with capsense , psoc4 . in addition, psoc designer offers a device selection tool at the time of creating a new project. application notes: cypress offers capsense application notes covering a broad range of topics, from basic to advanced level. recommended application notes for getting started with capsense are: ? an64846 : getting started with capsense ? an73034 : cy8c20xx6a/h/as capsense ? design guide ? an2397 : capsense? data viewing tools technical reference manual (trm): ? psoc? cy8c20xx6a/as/l family technical reference manual development kits: ? cy3280-20x66 universal capsense controller kit features a predefined control circuitry and plug-in hardware to make prototyping and debugging easy. programming and i2c-to-usb bridge hardware are included for tuning and data acquisition. ? cy3280-bmm matrix button module kit consists of eight capsense sensors organized in a 4x4 matrix format to form 16 physical buttons and eight leds. this module connects to any cy3280 universal capsense controller board, including cy3280-20x66 universal capsense controller. ? cy3280-bsm simple button module kit consists of ten capsense buttons and ten leds. this module connects to any cy3280 universal capsense controller board, including cy3280-20x66 universal capsense controller. the cy3217-miniprog1 and cy8ckit-002 psoc? miniprog3 device provides an interface for flash programming. psoc designer psoc designer is a free windows-based integrated design environment (ide). it enables concurrent hardware and firmware design of systems based on capsense (see figure 1 ). with psoc designer, you can: 1. drag and drop user modules to build your hardware system design in the main design workspace 2. codesign your application firm ware with the psoc hardware, using the psoc designer ide c compiler 3. configure user module 4. explore the library of user modules 5. review user module datasheets figure 1. psoc designer features 1 2 3 4 5
cy8c20xx6a/s document number: 001-54459 rev. *v page 4 of 52 contents psoc ? functional overview............................................ 5 psoc core .................................................................. 5 capsense system....................................................... 5 additional system resources . .................................... 6 getting started.................................................................. 7 capsense design guides ........................................... 7 silicon errata ............................................................... 7 development kits ........................................................ 7 training ....................................................................... 7 cypros consultants .................................................... 7 solutions library.......................................................... 7 technical support ....................................................... 7 development tools .......................................................... 8 psoc designer software subsyst ems............. ........... 8 designing with psoc designer ....................................... 9 select user modules ................................................... 9 configure user modules.......... .................................... 9 organize and connect ............... .............. .............. ..... 9 generate, verify, and debug....................................... 9 pinouts ............................................................................ 10 16-pin qfn (10 sensing inputs)[3, 4] ....................... 10 24-pin qfn (17 sensing inputs) [7]........................... 11 24-pin qfn (15 sensing inputs (with usb)) [11]...... 12 30-ball wlcsp (24 sensing inputs) [15]................... 13 32-pin qfn (25 sensing inputs) [18]......................... 14 32-pin qfn (22 sensing inputs (with usb)) [22]...... 15 48-pin ssop (31 sensing inputs) [26] ...................... 16 48-pin qfn (33 sensing inputs) [29]......................... 17 48-pin qfn (33 sensing inputs (with usb)) [33]...... 18 48-pin qfn (ocd) (33 sensing inputs) [37] ............. 19 electrical specifications ................................................ 20 absolute maximum ratings..... .................................. 20 operating temperature ............................................. 20 dc chip-level specifications.................................... 21 dc gpio specifications ............................................ 22 dc analog mux bus specificat ions........................... 24 dc low power comparator sp ecifications ............... 24 comparator user module elec trical specifications ... 25 adc electrical specifications .................................... 25 dc por and lvd specifications .............................. 26 dc programming specifications ............................... 26 dc i2c specifications ............................................... 27 dc reference buffer specificat ions.......................... 27 dc idac specifications ............................................ 27 ac chip-level specifications .................................... 28 ac gpio specifications ............................................ 29 ac comparator specifications .................................. 30 ac external clock specifications .............................. 30 ac programming specifications ................................ 31 ac i2c specifications................................................ 32 packaging information................................................... 35 thermal impedances................................................. 38 capacitance on crystal pins .... ............... .............. .... 38 solder reflow specifications.. ................................... 38 development tool selection ...... .............. .............. ....... 39 software .................................................................... 39 development kits ...................................................... 39 evaluation tools........................................................ 39 device programmers................ ................................. 39 accessories (emulation and programming) .............. 40 third party tools ....................................................... 40 build a psoc emulator into yo ur board.................... 40 ordering information...................................................... 41 ordering code definitions ...... ................................... 43 acronyms ........................................................................ 44 reference documents.................................................... 44 document conventions ................................................. 44 units of measure ....................................................... 44 numeric naming........................................................ 45 glossary .......................................................................... 45 errata ............................................................................... 46 qualification status ................................................... 46 errata summary ........................................................ 46 document history page ................................................. 49 sales, solutions, and legal information ...................... 52 worldwide sales and design supp ort............. .......... 52 products .................................................................... 52 psoc? solutions ...................................................... 52 cypress developer community................................. 52 technical support .................. ................................... 52
cy8c20xx6a/s document number: 001-54459 rev. *v page 5 of 52 psoc ? functional overview the psoc family consists of on-chip controller devices, which are designed to replace multiple traditional microcontroller unit (mcu)-based components with one, low cost single-chip programmable component. a psoc device includes configurable analog and digital blocks, and programmable interconnect. this architecture allows the user to create customized peripheral configurat ions, to match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts. the architecture for this device family, as shown in the logic block diagram on page 2 , consists of three main areas: the core capsense analog system system resources (including a full-speed usb port). a common, versatile bus allows connection between i/o and the analog system. each cy8c20xx6a/s psoc devi ce includes a dedicated capsense block that provides sensing and scanning control circuitry for capacitive sensing applications. depending on the psoc package, up to 36 gpio are also included. the gpio provides access to the mcu and analog mux. psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo and ilo. the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a 4-mips, 8-bit harvard-architecture microprocessor. capsense system the analog system contains the capacitive sensing hardware. several hardware algorithms are supported. this hardware performs capacitive sensing and scanning without requiring external components. the analog system is composed of the capsense psoc block and an internal 1 v or 1.2 v analog reference, which together support capacitive sensing of up to 33 inputs [2] . capacitive sensing is configurable on each gpio pin. scanning of enabled capsense pins are completed quickly and easily across multiple ports. smartsense smartsense is an innovative solution from cypress that removes manual tuning of capsense applications. this solution is easy to use and provides a robust noise immunity. it is the only auto-tuning solution that establishes, monitors, and maintains all required tuning parameters. smartsense allows engineers to go from prototyping to mass production without re-tuning for manufacturing variations in pcb and/or overlay material properties. smartsense_emc in addition to the smartsense auto tuning algorithm to remove manual tuning of capsense applications, smartsense_emc user module incorporates a unique algorithm to improve robustness of capacitive sensing algorithm/circuit against high frequency conducted and radiated noise. every electronic device must comply with specific lim its for radiated and conducted external noise and these limits are specified by regulatory bodies (for example, fcc, ce, u/l and so on). a very good pcb layout design, power supply design and system design is a mandatory for a product to pass the conducted and radiated noise tests. an ideal pcb layout, power supply design or system design is not often possible because of cost and form factor limitations of the product. smartsense_emc with s uperior noise immunity is well suited and handy for such applications to pass radiated and conducted noise test. figure 2. capsense system block diagram idac reference buffer vr cinternal analog global bus cap sense counters comparator mux mux refs capsense clock select oscillator csclk imo cs1 cs2 csn cexternal (p0[1] or p0[3]) note 2. 36 gpios = 33 pins for capacitive sensing + 2 pins for i 2 c + 1 pin for modulator capacitor.
cy8c20xx6a/s document number: 001-54459 rev. *v page 6 of 52 analog multiplexer system the analog mux bus can connect to every gpio pin. pins are connected to the bus individually or in any combination. the bus also connects to the analo g system for analysis with the capsense block comparator. switch control logic enables selected pins to precharge continuously under hardware control. this enables capacitive measurement for applications su ch as touch sensing. other multiplexer applications include: complex capacitive sensing in terfaces, such as sliders and touchpads. chip-wide mux that allows analog input from any i/o pin. crosspoint connection between any i/o pin combinations. additional system resources system resources provide additional capability, such as configurable usb and i 2 c slave, spi master/slave communication interface, three 16-bit programmable timers, and various system resets supported by the m8c. these system resources provide additional capabi lity useful to complete systems. additional resources include low voltage detection and power on reset. the merits of each system resource are listed here: the i 2 c slave/spi master-slave module provides 50/100/400 khz communication over two wires. spi communication over three or f our wires runs at speeds of 46.9 khz to 3 mhz (lower for a slower system clock). low-voltage detection (lvd) interrupts can signal the application of falling voltage levels, while the advanced power-on-reset (por) circuit e liminates the need for a system supervisor. an internal reference provides an absolute reference for capacitive sensing. a register-controlled bypass mode allows the user to disable the ldo regulator.
cy8c20xx6a/s document number: 001-54459 rev. *v page 7 of 52 getting started the quickest way to understand psoc silicon is to read this datasheet and then use the psoc designer integrated development environment (ide). this datasheet is an overview of the psoc integrated circuit and pr esents specific pin, register, and electrical specifications. for in depth information, along with detailed programming details, see the technical reference manual for the cy8c20xx6a/s psoc devices. for up-to-date ordering, packaging, and electrical specification information, see the latest ps oc device datasheets on the web at www.cypress.com/psoc . capsense design guides design guides are an excellent introduction to the wide variety of possible capsense designs. they are located at www.cypress.com/go/c apsensedesignguides . refer getting started with capsense design guide for information on capsense design and cy8c20xx6a/h/as capsense ? design guide for specific information on cy8c20xx6a/as capsense controllers. silicon errata errata documents known issues with silicon including errata trigger conditions, scope of impact, available workarounds and silicon revision applicability. refer to silicon errata for the psoc ? cy8c20x36a/46a/66a/96a/46 as/66as/36h/46h families available at http://www.cypress. com/?rid=56239 for errata information on cy8c20xx6a/as/h family of device. compare errata document with datasheet for a complete functional description of device. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics a nd skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736.
cy8c20xx6a/s document number: 001-54459 rev. *v page 8 of 52 development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application requirements. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical us er interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/transmitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a base device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are analog-to-digital converters (adcs), digital-to-analog converters (dacs), amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this lets you to use more than 100 percent of psoc?s resources for an application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs fo r the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu regist ers, set and clear breakpoints, and provide program run, halt , and step control. the debugger also lets you to create a trace buffer of registers and memory locations of interest. online help system the online help system displays online, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-se nsitive help. th is system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a ba se unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full-speed (24 mhz) operation.
cy8c20xx6a/s document number: 001-54459 rev. *v page 9 of 52 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed-function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of use r-selectable functions. the psoc development process is: 6. select user modules . 7. configure user modules. 8. organize and connect. 9. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules?. user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pwm user module configures one or more digital psoc blocks, one for each eight bits of resolution. using these parameters, you can establish the pulse width an d duty cycle. configure the parameters and properties to correspond to your chosen application. enter values directly or by selecting values from drop-down menus. all of the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the user module and provide performance specifications. each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. organize and connect build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate configuration files? step. this causes psoc designer to generate source code that automat ically configures the device to your specification and provides the software for the system. the generated code provides apis with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. a complete code development en vironment lets you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer?s debugger (accessed by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full-speed. psoc designer debugging capabilities rival those of syst ems costing many times more. in addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. it lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals.
cy8c20xx6a/s document number: 001-54459 rev. *v page 10 of 52 pinouts the cy8c20xx6a/s psoc device is available in a variety of pack ages, which are listed and illustrated in the following tables. e very port pin (labeled with a ?p?) is capable of digital i/o and connection to the common analog bus. however, v ss , v dd , and xres are not capable of digital i/o. 16-pin qfn (10 sensing inputs) [3, 4] table 1. pin definitions ? cy8c20 236a, cy8c20246a, cy8c20246as psoc device pin no. type name description figure 3. cy8c20236a, cy8c20246a, cy8c20246as digital analog 1 i/o i p2[5] crystal output (xout) 2 i/o i p2[3] crystal input (xin) 3 iohr i p1[7] i 2 c scl, spi ss 4 iohr i p1[5] i 2 c sda, spi miso 5 iohr i p1[3] spi clk 6 iohr i p1[1] issp clk [5] , i 2 c scl, spi mosi 7 power v ss ground connection 8 iohr i p1[0] issp data [5] , i 2 c sda, spi clk [6] 9 iohr i p1[2] 10 iohr i p1[4] optional external clock (extclk) 11 input xres active high external reset with internal pull-down 12 ioh i p0[4] 13 power v dd supply voltage 14 ioh i p0[7] 15 ioh i p0[3] integrating input 16 ioh i p0[1] integrating input legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. qfn ( top view ) ai , xout, p2[5] ai , i2 c scl, spi ss, p1[7] ai , i2 c sda, spi miso, p1[5] ai, spi cl k ,p1[3] 1 2 3 4 11 10 9 16 15 14 13 p0[3], ai p0[7], ai vdd p0[4] , ai ai, issp clk, spi mosi, p1[1] ai, issp data , i2c sda, spi cl k ,p1[0] p1[2] , ai ai , xin, p2[3] p1[4] , extclk, ai xres p0[1], ai vss 12 5 6 7 8 [5] [5,6] notes 3. 13 gpios = 10 pins for capacitive sensing + 2 pins for i2c + 1 pin for modulation capacitor. 4. no center pad. 5. on power-up, the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep c lock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 6. alternate spi clock.
cy8c20xx6a/s document number: 001-54459 rev. *v page 11 of 52 24-pin qfn (17 sensing inputs) [7] table 2. pin definitions ? cy8c20336a, cy8c20346a, cy8c20346as [8] pin no. type name description figure 4. cy8c20336a, cy8c20346a, cy8c20346as digital analog 1 i/o i p2[5] crystal output (xout) 2 i/o i p2[3] crystal input (xin) 3 i/o i p2[1] 4 iohr i p1[7] i 2 c scl, spi ss 5 iohr i p1[5] i 2 c sda, spi miso 6 iohr i p1[3] spi clk 7 iohr i p1[1] issp clk [9] , i 2 c scl, spi mosi 8 nc no connection 9 power v ss ground connection 10 iohr i p1[0] issp data [9] , i 2 c sda, spi clk [10] 11 iohr i p1[2] 12 iohr i p1[4] optional external clock input (extclk) 13 iohr i p1[6] 14 input xres active high external reset with internal pull-down 15 i/o i p2[0] 16 ioh i p0[0] 17 ioh i p0[2] 18 ioh i p0[4] 19 ioh i p0[6] 20 power v dd supply voltage 21 ioh i p0[7] 22 ioh i p0[5] 23 ioh i p0[3] integrating input 24 ioh i p0[1] integrating input cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. ai, issp data 2 , i2c sda, spi clk, p1[0] qfn (top view) ai, i2c scl, spi ss, p1[7] ai, i2c sda, spi miso, p1[5] ai, spi clk, p1[3] 1 2 3 4 5 6 18 17 16 15 14 13 p0[2], ai p0[0], ai 24 23 22 21 20 19 p0[3], ai p0[5], ai p0[7], ai vdd p0[4], ai 7 8 9 10 11 12 spi mosi, p1[1] ai, p1[2] ai, p2[1] nc p1[6], ai ai, extclk, p1[4] xres p2[0], ai p0[6], ai ai, issp clk 2 , i2c scl p0[1], ai vss ai, xout, p2[5] ai, xin, p2[3] [9, 10] notes 7. 20 gpios = 17 pins for capacitive sensing + 2 pins for i2c + 1 pin for modulation capacitor. 8. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 9. on power-up, the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep c lock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 10. alternate spi clock.
cy8c20xx6a/s document number: 001-54459 rev. *v page 12 of 52 24-pin qfn (15 sensing inputs (with usb)) [11] table 3. pin definitions ? cy8c20396a [12] pin no. type name description figure 5. cy8c20396a digital analog 1 i/o i p2[5] 2 i/o i p2[3] 3 i/o i p2[1] 4 iohr i p1[7] i 2 c scl, spi ss 5 iohr i p1[5] i 2 c sda, spi miso 6 iohr i p1[3] spi clk 7 iohr i p1[1] issp clk [13] , i 2 c scl, spi mosi 8power v ss ground 9 i/o i d+ usb d+ 10 i/o i d- usb d- 11 power v dd supply 12 iohr i p1[0] issp data [13] , i 2 c sda, spi clk [14] 13 iohr i p1[2] 14 iohr i p1[4] optional external clock input (extclk) 15 iohr i p1[6] 16 reset input xres active high external reset with internal pull-down 17 ioh i p0[0] 18 ioh i p0[2] 19 ioh i p0[4] 20 ioh i p0[6] 21 ioh i p0[7] 22 ioh i p0[5] 23 ioh i p0[3] integrating input 24 ioh i p0[1] integrating input cp power v ss center pad must be connected to ground legend i = input, o = output, oh = 5 ma high output drive, r = regulated output p0[7], ai ai, i2 c sda , spi miso , p1[5] d- qfn (top view) ai, i 2 c scl, spi ss, p1[7] ai, spi clk , p1[3] 1 2 3 4 5 6 18 17 16 15 14 13 p0[0], ai xres 24 23 22 21 20 19 p0[3], ai p0[5] p0[6], ai p0[2], ai 7 8 9 10 11 12 ai, issp clk, i2c scl, spi mosi, p1[1] vdd p2 [ 1] , a i vss p1[2 ], ai ai, issp data , i2c sda, spi clk, p1[0] p1[4] , ai, extclk p1[6], ai p0[4], ai p0[1], ai d+ p2 [ 5 ], ai p2 [ 3], ai , ai [13, [1 notes 11. 20 gpios = 15 pins for capacitive sensing + 2 pins fo r i2c + 2 pins for usb + 1 pin for modulation capacitor. 12. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 13. on power-up, the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 14. alternate spi clock.
cy8c20xx6a/s document number: 001-54459 rev. *v page 13 of 52 30-ball wlcsp (24 sensing inputs) [15] table 4. pin definitions ? cy8c 20766a, cy8c20746a 30-ball wlcsp pin no. type name description digital analog a1 ioh i p0[2] figure 6. cy8c20766a 30-ball wlcsp a2 ioh i p0[6] bottom view top view a3 power v dd supply voltage a4 ioh i p0[1] integrating input a5 i/o i p2[7] b1 i/o i p2[6] b2 ioh i p0[0] b3 ioh i p0[4] b4 ioh i p0[3] integrating input b5 i/o i p2[5] crystal output (xout) c1 i/o i p2[2] c2 i/o i p2[4] c3 ioh i p0[7] c4 ioh i p0[5] c5 i/o i p2[3] crystal input (xin) d1 i/o i p2[0] d2 i/o i p3[0] d3 i/o i p3[1] d4 i/o i p3[3] d5 i/o i p2[1] e1 input xres active high external reset with internal pull-down e2 iohr i p1[6] e3 iohr i p1[4] optional external clock input (ext clk) e4 iohr i p1[7] i 2 c scl, spi ss e5 iohr i p1[5] i 2 c sda, spi miso f1 iohr i p1[2] f2 iohr i p1[0] issp data [16] , i 2 c sda, spi clk [17] f3 power v ss supply ground f4 iohr i p1[1] issp clk [16] , i 2 c scl, spi mosi f5 iohr i p1[3] spi clk 54321 a b c d e f 12345 b c d e f a notes 15. 27 gpios = 24 pins for capacitive sensing + 2 pins for i2c + 1 pin for modulation capacitor. 16. on power-up , the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 17. alternate spi clock.
cy8c20xx6a/s document number: 001-54459 rev. *v page 14 of 52 32-pin qfn (25 sensing inputs) [18] table 5. pin definitions ? cy8c20436a, cy 8c20446a, cy8c20446as, cy8c20466a, cy8c20466as [19] pin no. type name description figure 7. cy8c20436a, cy8c20446a, cy8c20446as, cy8c20466a, cy8c20466as digital analog 1 ioh i p0[1] integrating input 2 i/o ip2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o ip3[3] 7 i/o i p3[1] 8 iohr i p1[7] i 2 c scl, spi ss 9 iohr i p1[5] i 2 c sda, spi miso 10 iohr i p1[3] spi clk. 11 iohr i p1[1] issp clk [20] , i 2 c scl, spi mosi. 12 power v ss ground connection. 13 iohr i p1[0] issp data [20] , i 2 c sda, spi clk [21] 14 iohr i p1[2] 15 iohr i p1[4] optional external clock input (extclk) 16 iohr i p1[6] 17 input xres active high external reset with internal pull-down 18 i/o ip3[0] 19 i/o ip3[2] 20 i/o ip2[0] 21 i/o i p2[2] 22 i/o i p2[4] 23 i/o i p2[6] 24 ioh i p0[0] 25 ioh i p0[2] 26 ioh i p0[4] 27 ioh i p0[6] 28 power v dd supply voltage 29 ioh i p0[7] 30 ioh i p0[5] 31 ioh i p0[3] integrating input 32 power v ss ground connection cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. ai , p0[1] ai , p2[7] ai , xout, p2[5] ai , xin, p2[3] ai , p2[1] ai , p3[3] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0 [3 ], ai p0 [7 ], ai vd d p0 [6 ], ai p0 [4 ], ai p0 [2 ], ai ai , p3[1] ai , i2 c scl, spi ss, p1[7] p0[0] , ai p2[6] , ai p3[0] , ai xres ai, i 2c sda, sp i miso, p 1[5] ai, spi clk, p1[3] vss ai, p 1[ 2] ai, e xtclk , p 1[ 4] ai, p 1[ 6] p2[4] , ai p2[2] , ai p2[0] , ai p3[2] , ai p0 [5 ], ai ai , issp clk , i2c scl, spi mosi, p1[1] ai , issp d ata , i2c sda, spi clk, p1[0] [20] [20] notes 18. 28 gpios = 25 pins for capacitive sensing + 2 pins for i2c + 1 pin for modulation capacitor. 19. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 20. on power-up, the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 21. alternate spi clock.
cy8c20xx6a/s document number: 001-54459 rev. *v page 15 of 52 32-pin qfn (22 sensing inputs (with usb)) [22] table 6. pin definitions ? cy8c20496a [23] pin no. type name description figure 8. cy8c20496a digital analog 1 ioh i p0[1] integrating input 2 i/o i p2[5] xtal out 3 i/o i p2[3] xtal in 4 i/o i p2[1] 5 iohr i p1[7] i 2 c scl, spi ss 6 iohr ip1[5]i 2 c sda, spi miso 7 iohr i p1[3] spi clk 8 iohr i p1[1] issp clk [24] , i 2 c scl, spi mosi 9 power v ss ground pin 10 i i d+ usb d+ 11 d- usb d- 12 power v dd power pin 13 iohr i p1[0] issp data [24] , i 2 c sda, spi clki [25] 14 iohr i p1[2] 15 iohr i p1[4] optional external clock input (extclk) 16 iohr i p1[6] 17 input xres active high external reset with internal pull-down 18 i/o ip3[0] 19 i/o ip3[2] 20 i/o ip2[0] 21 i/o i p2[2] 22 i/o i p2[4] 23 i/o i p2[6] 24 ioh i p0[0] 25 ioh i p0[2] 26 ioh i p0[4] 27 ioh i p0[6] 28 power v dd power pin 29 ioh i p0[7] 30 ioh i p0[5] 31 ioh i p0[3] integrating input 32 power v ss ground pin legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. ai , p 0[ 1 ] xtal out , p 2 [ 5 ] xtal in , p2 [ 3 ] ai , p2 [ 1 ] i2c scl, spi ss , p 1[ 7] i2c sda, spi miso , p 1[ 5 ] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0 [3 ], ai p0 [7 ], ai vd d p0 [6 ], ai p0 [4 ], ai p0 [2 ], ai spi clk , p1 [3 ] issp clk, i2c scl, spi mosi,p1 [ 1 ] p0[0] , ai p2[6] , ai p3[0] , ai xres vss usb phy, d+ vd d ai, p 1[ 2] ai, e xtclk , p 1[ 4] ai, p 1[ 6] p2[4] , ai p2[2] , ai p2[0] , ai p3[2] , ai p0 [5 ], ai usb d- issp , d ata, i2c sda, spi clk, p1[0] [24, 25] [24] notes 22. 27 gpios = 22 pins for capacitive sensing + 2 pins fo r i2c + 2 pins for usb + 1 pin for modulation capacitor. 23. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 24. on power-up, the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 25. alternate spi clock.
cy8c20xx6a/s document number: 001-54459 rev. *v page 16 of 52 48-pin ssop (31 sensing inputs) [26] table 7. pin definitions ? cy8c20536a, cy8c20546a, and cy8c20566a [27] pin no. digital analog name description figure 9. cy8c20536a, cy8c20546a, and cy8c20566a 1 ioh i p0[7] 2 ioh i p0[5] 3 ioh i p0[3] integrating input 4 ioh i p0[1] integrating input 5 i/o i p2[7] 6 i/o i p2[5] xtal out 7 i/o i p2[3] xtal in 8 i/o i p2[1] 9 nc no connection 10 nc no connection 11 i/o i p4[3] 12 i/o i p4[1] 13 nc no connection 14 i/o i p3[7] 15 i/o i p3[5] 16 i/o i p3[3] 17 i/o i p3[1] 18 nc no connection 19 nc no connection 20 iohr i p1[7] i 2 c scl, spi ss 21 iohr i p1[5] i 2 c sda, spi miso 22 iohr i p1[3] spi clk 23 iohr i p1[1] issp clk [27] , i 2 c scl, spi mosi 24 v ss ground pin 25 iohr i p1[0] issp data [27] , i 2 c sda, spi clk [28] 26 iohr i p1[2] 27 iohr i p1[4] optional external clock input (ext clk) 28 iohr i p1[6] 29 nc no connection 30 nc no connection 31 nc no connection 32 nc no connection pin no. digital analog name description 33 nc no connection 41 i/o i p2[2] 34 nc no connection 42 i/o i p2[4] 35 xres active high external reset with internal pull-down 43 i/o i p2[6] 36 i/o i p3[0] 44 ioh i p0[0] 37 i/o i p3[2] 45 ioh i p0[2] 38 i/o i p3[4] 46 ioh i p0[4] vref 39 i/o i p3[6] 47 ioh i p0[6] 40 i/o i p2[0] 48 power v dd power pin legend a = analog, i = input, o = output, nc = no connection, h = 5 ma high output drive, r = regulated output option. ssop ai, p0[7] vdd ai, p0[5] p0[6] , ai ai , p0[3] p0[4] , ai ai p0[1] p0[2] , ai ai , p2[7] p0[0] , ai xtalout, p2[5] p2[6] , ai xtalin, p2[3] p2[4] , ai ai , p2[1] p2[2] , ai nc p2[0] , ai nc p3[6] , ai ai, p4[3] p3[4] , ai ai, p4[1] p3[2] , ai nc p3[0] , ai ai, p3[7] xres ai , p3[5] nc ai , p3[3] nc ai , p3[1] nc nc nc nc nc i2 c scl, spi ss, p1[7] nc i2 c sda, spi miso, p1[5 ] p1[6] , ai spi clk, p1[3] p1[4] , ext clk issp clk, i2 c scl, spi mosi, p1[1 ] p1[2] , ai vss p1[0] , issp data, i2c sda, spi clk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 43 44 42 40 41 39 38 37 36 35 33 34 32 31 30 29 28 27 26 25 [27, 28] [27] notes 26. 34 gpios = 31 pins for capacitive sensing + 2 pins for i2c + 1 pin for modulation capacitor. 27. on power-up, the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 28. alternate spi clock.
cy8c20xx6a/s document number: 001-54459 rev. *v page 17 of 52 48-pin qfn (33 sensing inputs) [29] table 8. pin definitions ? cy8c20636a [30, 31] pin no. digital analog name description figure 10. cy8c20636a 1 nc no connection 2 i/o i p2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o i p4[3] 7 i/o ip4[1] 8 i/o i p3[7] 9 i/o i p3[5] 10 i/o i p3[3] 11 i/o i p3[1] 12 iohr i p1[7] i 2 c scl, spi ss 13 iohr i p1[5] i 2 c sda, spi miso 14 nc no connection 15 nc no connection 16 iohr i p1[3] spi clk 17 iohr i p1[1] issp clk [30] , i 2 c scl, spi mosi 18 power v ss ground connection 19 dnu 20 dnu 21 power v dd supply voltage 22 iohr i p1[0] issp data [30] , i 2 c sda, spi clk [32] 23 iohr i p1[2] 24 iohr i p1[4] optional external clock input (extclk) 25 iohr i p1[6] 26 input xres active high external reset with internal pull-down 27 i/o i p3[0] 28 i/o ip3[2] 29 i/o ip3[4] pin no. digital analog name description 30 i/o ip3[6] 40 ioh i p0[6] 31 i/o i p4[0] 41 power v dd supply voltage 32 i/o i p4[2] 42 nc no connection 33 i/o i p2[0] 43 nc no connection 34 i/o i p2[2] 44 ioh i p0[7] 35 i/o i p2[4] 45 ioh i p0[5] 36 i/o i p2[6] 46 ioh i p0[3] integrating input 37 ioh i p0[0] 47 power v ss ground connection 38 ioh i p0[2] 48 ioh i p0[1] 39 ioh i p0[4] cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive, r = regulated output. qfn (top view) vss p0[3], ai p0[5 ], ai p0[7], ai vdd p0[6], ai p0[2], ai p0[0], ai 10 11 12 ai , p2[7] nc ai , xout, p2[5] ai , xin , p2[3] ai , p2[1] ai , p4[3] ai , p4[1] ai , p3[7] ai , p3[5] ai , p3[3] ai p 3[1] ai , i2 c scl, spi ss, p1[7] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 4 6 45 44 43 42 41 4 0 39 38 37 p2[4] , ai p2[2] , ai p2[0] , ai p4[2] , ai p4[0] , ai p3[6] , ai p3[4] , ai p3[2] , ai p3[0 ], ai xres p1[6] , ai p2[6] , ai 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 i2c sda, spi miso, a i, p1[5] nc spiclk,ai,p1[3] ai , issp cl k , i2c scl, spi mosi, p1[1] vss dnu dnu vdd ai, issp data 1 ,i2csda,spicl k , p1[0] ai, p 1[ 2] ai, extclk, p1[4] nc nc nc p0[4], ai p0[1], ai [30] [30, 32] notes 29. 36 gpios = 33 pins for capacitive sensing + 2 pins for i2c + 1 pin for modulation capacitor. 30. on power-up, the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 31. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal 32. alternate spi clock.
cy8c20xx6a/s document number: 001-54459 rev. *v page 18 of 52 48-pin qfn (33 sensing inputs (with usb)) [33] table 9. pin definitions ? cy8c20646 a, cy8c20646as, cy8c20666a, cy8c20666as [34, 35] pin no. digital analog name description figure 11. cy8c20646a, cy8c20646as, cy8c20666a, cy8c20666as 1 nc no connection 2 i/o i p2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o i p4[3] 7 i/o i p4[1] 8 i/o i p3[7] 9 i/o i p3[5] 10 i/o i p3[3] 11 i/o i p3[1] 12 iohr i p1[7] i 2 c scl, spi ss 13 iohr i p1[5] i 2 c sda, spi miso 14 nc no connection 15 nc no connection 16 iohr i p1[3] spi clk 17 iohr i p1[1] issp clk [34] , i 2 c scl, spi mosi 18 power v ss ground connection 19 i/o d+ usb d+ 20 i/o d- usb d- 21 power v dd supply voltage 22 iohr i p1[0] issp data [34] , i 2 c sda, spi clk [36] 23 iohr i p1[2] 24 iohr i p1[4] optional external clock input (extclk) 25 iohr i p1[6] 26 input xres active high external reset with internal pull-down 27 i/o i p3[0] 28 i/o i p3[2] 29 i/o i p3[4] pin no. digital analog name description 30 i/o i p3[6] 40 ioh i p0[6] 31 i/o i p4[0] 41 power v dd supply voltage 32 i/o i p4[2] 42 nc no connection 33 i/o i p2[0] 43 nc no connection 34 i/o i p2[2] 44 ioh i p0[7] 35 i/o i p2[4] 45 ioh i p0[5] 36 i/o i p2[6] 46 ioh i p0[3] integrating input 37 ioh i p0[0] 47 power v ss ground connection 38 ioh i p0[2] 48 ioh i p0[1] 39 ioh i p0[4] cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive, r = regulated output. qfn vss p0[3], ai p0[5 ], ai p0[7], ai vdd p0[6], ai p0[2], ai p0[0], ai ai , p2[7] nc ai , xout, p2[5] ai , xin , p2[3] ai , p2[1] ai , p4[3] ai , p4[1] ai , p3[7] ai , p3[5] ai , p3[3] ai , p3[1] ai , i2 c scl, spi ss, p1[7] 35 34 33 32 36 48 47 46 45 44 43 42 41 40 39 38 37 p2[4] , ai p2[2] , ai p2[0] , ai p4[2] , ai p2[6] , ai 1 2 3 4 5 nc nc p0[4], ai p0[1], ai (top view) 10 11 12 31 30 29 28 27 26 25 p4[0] , ai p3[6] , ai p3[4] , ai p3[2] , ai p3[0 ], ai xres p1[6] , ai 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 i2c sda, spi miso, a i, p1[5] nc spi clk, a i, p1[3] ai , issp cl k ,i2cscl,spimosi,p1[1] vss d+ d- vdd ai , issp data, i2c sda, spi cl k ,p1[0] ai, p 1[ 2 ] ai, extclk, p1[4] nc [34, 36] [34] notes 33. 38 gpios = 33 pins for capacitive sensing + 2 pins fo r i2c + 2 pins for usb + 1 pin for modulation capacitor. 34. on power-up, the sda(p1[0]) drives a strong high for 256 sle ep clock cycles and drives resistive low for the next 256 sleep clock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de- asserts , the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high imped ance state. in both cases, a pull-up resistance on these lin es combines with the pull-down resistance (5.6k ohm) and form a potential divider. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use al ternate pins if you encounter issues. 35. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 36. alternate spi clock.
cy8c20xx6a/s document number: 001-54459 rev. *v page 19 of 52 48-pin qfn (ocd) (33 sensing inputs) [37] the 48-pin qfn part is for the cy8c20066a on-chip debug (ocd). no te that this part is only used for in-circuit debugging. table 10. pin definitions ? cy8c20066a [38, 39] pin no. digital analog name description figure 12. cy8c20066a 1 [40] ocdoe ocd mode direction pin 2 i/o i p2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o i p4[3] 7 i/o i p4[1] 8 i/o i p3[7] 9 i/o i p3[5] 10 i/o i p3[3] 11 i/o i p3[1] 12 iohr i p1[7] i 2 c scl, spi ss 13 iohr i p1[5] i 2 c sda, spi miso 14 [40] cclk ocd cpu clock output 15 [40] hclk ocd high speed clock output 16 iohr i p1[3] spi clk. 17 iohr i p1[1] issp clk [ 41 ], i 2 c scl, spi mosi 18 power v ss ground connection 19 i/o d+ usb d+ 20 i/o d- usb d- 21 power v dd supply voltage 22 iohr i p1[0] issp data [ 41 ] , i 2 c sda, spi clk [ 42 ] 23 iohr i p1[2] pin no. digital analog name description 24 iohr i p1[4] optional external clock input (extclk) 37 ioh i p0[0] 25 iohr i p1[6] 38 ioh i p0[2] 26 input xres active high external reset with internal pull-down 39 ioh i p0[4] 27 i/o i p3[0] 40 ioh i p0[6] 28 i/o i p3[2] 41 power v dd supply voltage 29 i/o i p3[4] 42 [40] ocdo ocd even data i/o 30 i/o i p3[6] 43 [40] ocde ocd odd data output 31 i/o i p4[0] 44 ioh i p0[7] 32 i/o i p4[2] 45 ioh i p0[5] 33 i/o i p2[0] 46 ioh i p0[3] integrating input 34 i/o i p2[2] 47 power v ss ground connection 35 i/o i p2[4] 48 ioh i p0[1] 36 i/o i p2[6] cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive, r = regulated output. qfn (top view) vss p0[3], ai p0[5 ], ai p0[7], ai vdd p0[6], ai p0[2], ai p0[0], ai 10 11 12 a i , p2[7] ai , xout, p2[5] ai , xin , p2[3] ai , p2[1] ai , p4[3] ai , p4[1] ai , p3[7] ai , p3[5] ai , p3[3] ai , p3[1] ai , i2 c scl, spi ss, p1[7] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p2[4] , ai p2[2] , ai p2[0] , ai p4[2] , ai p4[0] , ai p3[6] , ai p3[4] , ai p3[2] , ai p3[0] , ai xres p1[6] , ai p2[6] , ai 1 2 3 4 5 6 7 8 9 1 3 14 15 16 17 18 19 20 21 22 23 24 i2c sda, spi miso, ai, p1[5] spi clk, a i, p1[3] ai , issp clk 6 , i2c scl, spi mosi, p1[1] vss d+ d- vdd ai,issp data 1 , i2c sda, spi clk, p1[0] ai, p 1 [ 2 ] ai, extclk, p1[4] p0[4], ai p0[1], ai ocdo e cclk hclk ocde ocdo [41, 42] [41] notes 37. 38 gpios = 33 pins for capacitive sensing + 2 pins fo r i2c + 2 pins for usb + 1 pin for modulation capacitor. 38. this part is available in limited quantities for in-circuit debugging during prototype development. it is not available in p roduction volumes. 39. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 40. this pin (associated with ocd part only) is required for connec ting the device to ice-cube in-circuit emulator for firmware debugging purpose. to know more about the usage of ice-cube, refer to cy3215-dk psoc ? in-circuit emulator kit guide . 41. on power-up, the sda(p1[0]) drives a strong high for 256 sle ep clock cycles and drives resistive low for the next 256 sleep clock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de- asserts , the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high imped ance state. in both cases, a pull-up resistance on these lin es combines with the pull-down resistance (5.6k ohm) and form a potential divider. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use al ternate pins if you encounter issues. 42. alternate spi clock.
cy8c20xx6a/s document number: 001-54459 rev. *v page 20 of 52 electrical specifications this section presents the dc and ac electrical specifications of the cy8c20xx6a/s psoc devices. for the latest electrical speci fi- cations, confirm that you have the most recent datasheet by visiting the web at http://www.cyp ress.com/psoc . figure 13. voltage versus cpu frequency absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. operating temperature 5.5v 750 khz 24 mhz cpu frequency vdd voltage 1.71v 3 mhz v a l i d o p e r a t i n g r e g i o n table 11. absolute maximum ratings symbol description conditions min typ max units t stg storage temperature higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temperatures above 85 c degrades reliability. ?55 +25 +125 c v dd supply voltage relative to v ss ? ?0.5 ? +6.0 v v io dc input voltage ? v ss ? 0.5 ? v dd + 0.5 v v ioz [43] dc voltage applied to tristate ? v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any port pin ? ?25 ? +50 ma esd electrostatic discharge voltage human body model esd 2000 ? ? v lu latch-up current in accordance with jesd78 standard ? ? 200 ma table 12. operating temperature symbol description conditions min typ max units t a ambient temperature ? ?40 ? +85 c t c commercial temperature range ? 0 70 c t j operational die temperature the temperature rise from ambient to junction is package specific. refer the thermal impedances on page 38 . the user must limit the power consumption to comply with this requirement. ?40 ? +100 c note 43. port1 pins are hot-swap capable with i/o configur ed in high-z mode, and pin input voltage above v dd .
cy8c20xx6a/s document number: 001-54459 rev. *v page 21 of 52 dc chip-level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 13. dc chip-level specifications symbol description conditions min typ max units v dd [44, 45, 46, 47] supply voltage no usb activity. refer the table ?dc por and lvd specifications? on page 26 1.71 ? 5.50 v v ddusb [44, 45, 46, 47] operating voltage usb activity, usb regulator enabled 4.35 ? 5.25 v usb activity, usb regulator bypassed 3.15 3.3 3.60 v i dd24 supply current, imo = 24 mhz conditions are v dd ? 3.0 v, t a = 25 c, cpu = 24 mhz. capsense running at 12 mhz, no i/o sourcing current ? 2.88 4.00 ma i dd12 supply current, imo = 12 mhz conditions are v dd ? 3.0 v, t a = 25 c, cpu = 12 mhz. capsense running at 12 mhz, no i/o sourcing current ? 1.71 2.60 ma i dd6 supply current, imo = 6 mhz conditions are v dd ? 3.0 v, t a = 25 c, cpu = 6 mhz. capsense running at 6 mhz, no i/o sourcing current ? 1.16 1.80 ma i ddavg10 average supply current per sensor one sensor scanned at 10 ms rate ? 250 ? ? a i ddavg100 average supply current per sensor one sensor scanned at 100 ms rate ? 25 ? ? a i ddavg500 average supply current per sensor one sensor scanned at 500 ms rate ? 7 ? ? a i sb0 [48, 49, 50, 51, 52, 53] deep sleep current v dd ? 3.0 v, t a = 25 c, i/o regulator turned off ? 0.10 1.05 ? a i sb1 [48, 49, 50, 51, 52, 53] standby current with por, lvd and sleep timer v dd ? 3.0 v, t a = 25 c, i/o regulator turned off ? 1.07 1.50 ? a i sbi2c [48, 49, 50, 51, 52, 53] standby current with i 2 c enabled conditions are v dd = 3.3 v, t a = 25 c and cpu = 24 mhz ? 1.64 ? ? a notes 44. when v dd remains in the range from 1.71 v to 1.9 v for more than 50 s, t he slew rate when moving from the 1.71 v to 1.9 v range to gre ater than 2 v must be slower than 1 v/500 s to avoid triggering por. the only other re striction on slew rates for any other voltage range or transit ion is the sr power_up parameter. 45. if powering down in standby sleep mode, to properly detect and recover from a v dd brown out condition any of the following actions must be taken: a.bring the device out of sleep before powering down. b.assure that v dd falls below 100 mv before powering back up. c.set the no buzz bit in the osc_cr0 register to k eep the voltage monitoring circuit powered during sleep. d.increase the buzz rate to assu re that the falling edge of v dd is captured. the rate is configured th rough the pssdc bits in the slp_cfg register. for the referenced registers, refer to the cy8c20x36 technical reference manual . in deep sleep mode, additional low power voltage monitoring circuitry allows v dd brown out conditions to be detected for edge rates slower than 1v/ms. 46. for usb mode, the v dd supply for bus-powered application should be limited to 4.35 v?5.35 v. for self-powered application, v dd should be 3.15 v?3.45 v. 47. for proper capsense block f unctionality, if the drop in v dd exceeds 5% of the base v dd , the rate at which v dd drops should not exceed 200 mv/s. base v dd can be between 1.8 v and 5.5 v. 48. errata: when the device is put to sleep in standby or i2c_usb mode a nd the bandgap circuit is refreshed less frequently than every 8 m s (default), the device may not come out of sleep when a sleep-ending input is received. for more information, see the ?errata? on page 46. 49. errata: the i2c block exhibits occasional data and bus corruption errors when the i2c master initiates transactions while the device is in or out of transition of sleep mode. for more information, see the ?errata? on page 46. 50. errata: when programmable timer 0 is used in ?one-s hot? mode by setting bit 1 of register 0, b0h (pt0_cfg), and the timer interrupt is u sed to wake the device from sleep, the interrupt service routine (isr) may be executed twice. for more information, see the ?errata? on page 47. 51. errata: when in sleep mode, if a gpio interrupt happens simultaneously with a timer0 or sleep timer interrupt, the gpio interrupt may b e missed, and the corresponding gpio isr not run. for more information, see the ?errata? on page 47. 52. errata: if an interrupt is posted a short time (within 2.5 cpu cycles) bef ore firmware commands the device to sleep, the interrupt will be missed. for more information, see the ?errata? on page 48. 53. errata: device wakes up from sleep when an analog interrupt is trigger. for more information, see the ?errata? on page 48.
cy8c20xx6a/s document number: 001-54459 rev. *v page 22 of 52 dc gpio specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 5.5 v and ?40 c ? t a ? 85 c, 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, or 1.71 v to 2.4 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 14. 3.0 v to 5.5 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k ? v oh1 high output voltage port 2 or 3 or 4 pins i oh < 10 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh2 high output voltage port 2 or 3 or 4 pins i oh = 1 ma, maximum of 20 ma source current in all i/os v dd ? 0.90 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh < 10 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 5 ma, maximum of 20 ma source current in all i/os v dd ? 0.90 ? ? v v oh5 high output voltage port 1 pins with ldo regulator enabled for 3 v out i oh < 10 ? a, v dd > 3.1 v, maximum of 4 i/os all sourcing 5 ma 2.85 3.00 3.30 v v oh6 high output voltage port 1 pins with ldo regulator enabled for 3 v out i oh = 5 ma, v dd > 3.1 v, maximum of 20 ma source current in all i/os 2.20 ? ? v v oh7 high output voltage port 1 pins with ldo enabled for 2.5 v out i oh < 10 ? a, v dd > 2.7 v, maximum of 20 ma source current in all i/os 2.35 2.50 2.75 v v oh8 high output voltage port 1 pins with ldo enabled for 2.5 v out i oh = 2 ma, v dd > 2.7 v, maximum of 20 ma source current in all i/os 1.90 ? ? v v oh9 high output voltage port 1 pins with ldo enabled for 1.8 v out i oh < 10 ? a, v dd > 2.7 v, maximum of 20 ma source current in all i/os 1.60 1.80 2.10 v v oh10 high output voltage port 1 pins with ldo enabled for 1.8 v out i oh = 1 ma, v dd > 2.7 v, maximum of 20 ma source current in all i/os 1.20 ? ? v v ol low output voltage i ol = 25 ma, v dd > 3.3 v, maximum of 60 ma sink current on even port pins (for example, p0[2] and p1[4]) and 60 ma sink current on odd port pins (for example, p0[3] and p1[5]) ??0.75v v il input low voltage ? ? ? 0.80 v v ih input high voltage ? 2.00 ? ? v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 0.001 1 ? a c pin pin capacitance package and pin dependent te m p = 2 5 c 0.50 1.70 7 pf v illvt3.3 input low voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 0.8 v ? ? v ihlvt3.3 input high voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 1.4 ? ? v v illvt5.5 input low voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 0.8 v ? ? v ihlvt5.5 input high voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 1.7 ? ? v
cy8c20xx6a/s document number: 001-54459 rev. *v page 23 of 52 table 15. 2.4 v to 3.0 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k ? v oh1 high output voltage port 2 or 3 or 4 pins i oh < 10 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh2 high output voltage port 2 or 3 or 4 pins i oh = 0.2 ma, maximum of 10 ma source current in all i/os v dd ? 0.40 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh < 10 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 2 ma, maximum of 10 ma source current in all i/os v dd ? 0.50 ? ? v v oh5a high output voltage port 1 pins with ldo enabled for 1.8 v out i oh < 10 ? a, v dd > 2.4 v, maximum of 20 ma source current in all i/os 1.50 1.80 2.10 v v oh6a high output voltage port 1 pins with ldo enabled for 1.8 v out i oh = 1 ma, v dd > 2.4 v, maximum of 20 ma source current in all i/os 1.20 ? ? v v ol low output voltage iol = 10 ma, maximum of 30 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.75 v v il input low voltage ? ? ? 0.72 v v ih input high voltage ? 1.40 ? v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 1 1000 na c pin capacitive load on pins package and pin dependent temp = 25 ? c 0.50 1.70 7 pf v illvt2.5 input low voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 0.7 v ? v ihlvt2.5 input high voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 1.2 ? v table 16. 1.71 v to 2.4 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k ? v oh1 high output voltage port 2 or 3 or 4 pins i oh = 10 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh2 high output voltage port 2 or 3 or 4 pins i oh = 0.5 ma, maximum of 10 ma source current in all i/os v dd ? 0.50 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 100 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 2 ma, maximum of 10 ma source current in all i/os v dd ? 0.50 ? ? v v ol low output voltage i ol = 5 ma, maximum of 20 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.40 v
cy8c20xx6a/s document number: 001-54459 rev. *v page 24 of 52 dc analog mux bus specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. dc low power compar ator spec ifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. v il input low voltage ? ? ? 0.30 v dd v v ih input high voltage ? 0.65 v dd ??v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 1 1000 na c pin capacitive load on pins package and pin dependent temp = 25 c 0.50 1.70 7 pf table 16. 1.71 v to 2.4 v dc gpio specifications (continued) symbol description conditions min typ max units table 17. dc characteristics ? usb interface symbol description conditions min typ max units r usbi usb d+ pull-up resistance with idle bus 900 ? 1575 ? r usba usb d+ pull-up resistance while receiving traffic 1425 ? 3090 ? v ohusb static output high ? 2.8 ?3.6v v olusb static output low ? ? ?0.3v v di differential input sensitivity ? 0.2 ?v v cm differential input common mode range ? 0.8 ?2.5v v se single ended receiver threshold ? 0.8 ?2.0v c in transceiver capacitance ? ? ?50pf i io high z state data line leakage on d+ or d- line ?10 ?+10 ? a r ps2 ps/2 pull-up resistance ? 3000 5000 7000 ? r ext external usb series resistor in se ries with each usb pin 21.78 22.0 22.22 ? table 18. dc analog mux bus specifications symbol description conditions min typ max units r sw switch resistance to common analog bus ? ? ? 800 ? r gnd resistance of initialization switch to v ss ? ? ? 800 ? the maximum pin voltage for measuring r sw and r gnd is 1.8 v table 19. dc comparator specifications symbol description conditions min typ max units v lpc low power comparator (lpc) common mode maximum voltage limited to v dd 0.0 ? 1.8 v i lpc lpc supply current ? ? 10 40 ? a v oslpc lpc voltage offset ? ? 3 30 mv
cy8c20xx6a/s document number: 001-54459 rev. *v page 25 of 52 comparator user module electrical sp ecifications the following table lists the guaranteed maximum and minimum spec ifications. unless stated otherwis e, the specifications are fo r the entire device voltage and temperature operating range: ?40 c ? t a ? 85 c, 1.71 v ? v dd ? 5.5 v. adc electrical specifications table 20. comparator user module electrical specifications symbol description conditions min typ max units t comp comparator response time 50 mv overdrive ? 70 100 ns offset valid from 0.2 v to v dd ? 0.2 v ? 2.5 30 mv current average dc current, 50 mv overdrive ? 20 80 a psrr supply voltage > 2 v power supply rejection ratio ? 80 ? db supply voltage < 2 v power supply rejection ratio ? 40 ? db input range ? 0 1.5 v table 21. adc user module electrical specifications symbol description conditions min typ max units input v in input voltage range ? 0 ? vrefadc v c iin input capacitance ???5pf r in input resistance equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution 1/(500ff data clock) 1/(400ff data clock) 1/(300ff data clock) ? reference v refadc adc reference voltage ? 1.14 ? 1.26 v conversion rate f clk data clock source is chip?s internal main oscillator. see ac chip-level specifications for accuracy 2.25 ? 6 mhz s8 8-bit sample rate data cl ock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) ? 23.43 ? ksps s10 10-bit sample rate data clock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) ? 5.85 ? ksps dc accuracy res resolution can be set to 8-, 9-, or 10-bit 8 ? 10 bits dnl differential nonlinearity ? ?1 ? +2 lsb inl integral nonlinearity ? ?2 ? +2 lsb e offset offset error 8-bit resolution 0 3.20 19.20 lsb 10-bit resolution 0 12.80 76.80 lsb e gain gain error for any re solution ?5 ? +5 %fsr power i adc operating current ? ? 2.10 2.60 ma psrr power supply rejection ratio psrr (v dd > 3.0 v) ? 24 ? db psrr (v dd < 3.0 v) ? 30 ? db
cy8c20xx6a/s document number: 001-54459 rev. *v page 26 of 52 dc por and lvd specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. dc programming specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 22. dc por and lvd specifications symbol description conditions min typ max units v por0 1.66 v selected in psoc designer v dd must be greater than or equal to 1.71 v during startup, reset from the xres pin, or reset from watchdog. 1.61 1.66 1.71 v v por1 2.36 v selected in psoc designer ? 2.36 2.41 v por2 2.60 v selected in psoc designer ? 2.60 2.66 v por3 2.82 v selected in psoc designer ? 2.82 2.95 v lvd0 2.45 v selected in psoc designer ? 2.40 2.45 2.51 v v lvd1 2.71 v selected in psoc designer 2.64 [54] 2.71 2.78 v lvd2 2.92 v selected in psoc designer 2.85 [55] 2.92 2.99 v lvd3 3.02 v selected in psoc designer 2.95 [56] 3.02 3.09 v lvd4 3.13 v selected in psoc designer 3.06 3.13 3.20 v lvd5 1.90 v selected in psoc designer 1.84 1.90 2.32 v lvd6 1.80 v selected in psoc designer 1.75 [57] 1.80 1.84 v lvd7 4.73 v selected in psoc designer 4.62 4.73 4.83 table 23. dc programming specifications symbol description conditions min typ max units v ddiwrite supply voltage for flash write operations ? 1.71 ? 5.25 v i ddp supply current during programming or verify ? ? 5 25 ma v ilp input low voltage during programming or verify see the appropriate dc gpio specifications on page 22 ? ? v il v v ihp input high voltage during programming or verify see the appropriate ?dc gpio specifications? on page 22 v ih ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify driving internal pull-down resistor ? ? 0.2 ma i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify driving internal pull-down resistor ? ? 1.5 ma v olp output low voltage during programming or verify ? ? v ss + 0.75 v v ohp output high voltage during programming or verify see appropriate dc gpio specifications on page 22 . for v dd > 3 v use v oh4 in table 12 on page 20. v oh ? v dd v flash enpb flash write endurance erase/write cycles per block 50,000 ? ? ? flash dr flash data retention following maximum flash write cycles; ambient temperature of 55 c 20 ? ? years notes 54. always greater than 50 mv above v ppor1 voltage for falling supply. 55. always greater than 50 mv above v ppor2 voltage for falling supply. 56. always greater than 50 mv above v ppor3 voltage for falling supply. 57. always greater than 50 mv above v ppor0 voltage for falling supply.
cy8c20xx6a/s document number: 001-54459 rev. *v page 27 of 52 dc i 2 c specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 5.5 v and ?40 c ? t a ? 85 c, 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, or 1.71 v to 2.4 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc reference buffer specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 5.5 v and ?40 c ? t a ? 85 c, 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, or 1.71 v to 2.4 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc idac specifications the following table lists guaranteed maximum and minimum spec ifications for the entire vo ltage and temperature ranges. table 24. dc i 2 c specifications symbol description conditions min typ max units v ili2c input low level 3.1 v v dd 5.5 v ? ? 0.25 v dd v 2.5 v v dd 3.0 v ? ? 0.3 v dd v 1.71 v v dd 2.4 v ? ? 0.3 v dd v v ihi2c input high level 1.71 v v dd 5.5 v 0.65 v dd ??v table 25. dc reference buffer specifications symbol description conditions min typ max units v ref reference buffer output 1.7 v v dd 5.5 v 1 ? 1.05 v v refhi reference buffer output 1.7 v v dd 5.5 v 1.2 ? 1.25 v table 26. dc idac specifications symbol description min typ max units notes idac_dnl differential nonlinearity ?4.5 ? +4.5 lsb idac_inl integral nonlinearity ?5 ? +5 lsb idac_gain (source) range = 0.5x 6.64 ? 22.46 a dac setting = 128 dec. not recommended for capsense applications. range = 1x 14.5 ? 47.8 a range = 2x 42.7 ? 92.3 a range = 4x 91.1 ? 170 a dac setting = 128 dec range = 8x 184.5 ? 426.9 a dac setting = 128 dec
cy8c20xx6a/s document number: 001-54459 rev. *v page 28 of 52 ac chip-level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 27. ac chip-level specifications symbol description conditions min typ max units f imo24 imo frequency at 24 mhz setting ? 22.8 24 25.2 mhz f imo12 imo frequency at 12 mhz setting ? 11.4 12 12.6 mhz f imo6 imo frequency at 6 mhz setting ? 5.7 6.0 6.3 mhz f cpu cpu frequency ? 0.75 ? 25.20 mhz f 32k1 ilo frequency ? 15 32 50 khz f 32k_u ilo untrimmed frequency ? 13 32 82 khz dc imo duty cycle of imo ? 40 50 60 % dc ilo ilo duty cycle ? 40 50 60 % sr power_up power supply slew rate v dd slew rate during power-up ? ? 250 v/ms t xrst external reset pulse width at power-up after supply voltage is valid 1 ? ? ms t xrst2 external reset pulse width after power-up [58] applies after part has booted 10 ? ? ? s t os startup time of eco ??1?s t jit_imo [59] n=32 6 mhz imo cycle-to-cycle jitter (rms) ? 0.7 6.7 ns 6 mhz imo long term n (n = 32) cycle-to-cycle jitter (rms) ? 4.3 29.3 ns 6 mhz imo period jitter (rms) ? 0.7 3.3 ns 12 mhz imo cycle-to-cycle jitter (rms) ? 0.5 5.2 ns 12 mhz imo long term n (n = 32) cycle-to-cycle jitter (rms) ?2.35.6ns 12 mhz imo period jitter (rms) ? 0.4 2.6 ns 24 mhz imo cycle-to-cycle jitter (rms) ? 1.0 8.7 ns 24 mhz imo long term n (n = 32) cycle-to-cycle jitter (rms) ?1.46.0ns 24 mhz imo period jitter (rms) ? 0.6 4.0 ns notes 58. the minimum required xres pulse length is longer when programming the device (see table 33 on page 31 ). 59. refer to cypress jitter specifications application note, understanding datasheet jitt er specifications for cypr ess timing products ? an5054 for more information.
cy8c20xx6a/s document number: 001-54459 rev. *v page 29 of 52 ac gpio specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. figure 14. gpio timing diagram table 28. ac gpio specifications symbol description conditions min typ max units f gpio gpio operating frequency normal strong mode port 0, 1 0 0 ? ? 6 mhz for 1.71 v cy8c20xx6a/s document number: 001-54459 rev. *v page 30 of 52 ac comparator specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. ac external clock specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 29. ac characteristics ? usb data timings symbol description conditions min typ max units t drate full speed data rate average bit rate 12 ? 0.25% 12 12 + 0.25% mhz t jr1 receiver jitter tolerance to next transition ?18.5 ? 18.5 ns t jr2 receiver jitter tolerance to pair transition ?9.0 ? 9 ns t dj1 fs driver jitter to next transition ?3.5 ? 3.5 ns t dj2 fs driver jitter to pair transition ?4.0 ? 4.0 ns t fdeop source jitter for differential transition to se0 transition ?2.0 ? 5 ns t feopt source se0 interval of eop ? 160.0 ? 175 ns t feopr receiver se0 interval of eop ? 82.0 ? ? ns t fst width of se0 interval during differential transition ???14ns table 30. ac characteristics ? usb driver symbol description conditions min typ max units t fr transition rise time 50 pf 4 ? 20 ns t ff transition fall time 50 pf 4 ? 20 ns t frfm [60] rise/fall time matching ? 90 ? 111 % v crs output signal crosso ver voltage ? 1.30 ? 2.00 v table 31. ac low power comparator specifications symbol description conditions min typ max units t lpc comparator response time, 50 mv overdrive 50 mv overdrive does not include offset voltage. ??100ns table 32. ac external clock specifications symbol description conditions min typ max units f oscext frequency (external oscillator frequency) ?0.75 ? 25.20 mhz high period ? 20.60 ? 5300 ns low period ? 20.60 ? ?ns power-up imo to switch ? 150 ? ? ? s note 60. t frfm is not met under all conditions. there is a corner case at lo wer supply voltages, such as thos e under 3.3 v. this condition do es not affect usb communications. signal integrity tests show an e xcellent eye diagram at 3.15 v.
cy8c20xx6a/s document number: 001-54459 rev. *v page 31 of 52 ac programming specifications figure 15. ac waveform the following table lists the guaranteed maximum and minimum s pecifications for the entire vo ltage and temperature ranges. table 33. ac programming specifications symbol description conditions min typ max units t rsclk rise time of sclk ? 1 ? 20 ns t fsclk fall time of sclk ? 1 ? 20 ns t ssclk data setup time to fa lling edge of sclk ? 40 ? ? ns t hsclk data hold time from falling edge of sclk ? 40 ? ? ns f sclk frequency of sclk ? 0 ? 8 mhz t eraseb flash erase time (block) ? ? ? 18 ms t write flash block write time ? ? ? 25 ms t dsclk data out delay from falling edge of sclk 3.6 ? v dd ? ? 60 ns t dsclk3 data out delay from falling edge of sclk 3.0 ? v dd ? 3.6 ? ? 85 ns t dsclk2 data out delay from falling edge of sclk 1.71 ? v dd ? 3.0 ? ? 130 ns t xrst3 external reset pulse width after power-up required to enter programming mode when coming out of sleep 300 ? ? ? s t xres xres pulse length ? 300 ? ? ? s t vddwait [61] v dd stable to wait-and-poll hold off ? 0.1 ? 1 ms t vddxres [61] v dd stable to xres assertion delay ? 14.27 ? ? ms t poll sdata high pulse time ? 0.01 ? 200 ms t acq [61] ?key window? time after a v dd ramp acquire event, based on 256 ilo clocks. ? 3.20 ? 19.60 ms t xresini [61] ?key window? time after an xres event, based on 8 ilo clocks ? 98 ? 615 ? s sclk (p1[1]) t rsclk t fsclk sdata (p1[0]) t ssclk t hsclk t dsclk note 61. valid from 5 to 50 c. see the spec, cy8c20x66, cy8c20x46, cy8c20x36, cy7c643xx, cy7c604xx, cy8ctst2xx, cy8ctmg2xx, cy8c20x6 7, cy8c20x47, cy8c20x37, programming spec for more details.
cy8c20xx6a/s document number: 001-54459 rev. *v page 32 of 52 ac i 2 c specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. figure 16. definition for timing for fast/standard mode on the i 2 c bus table 34. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units min max min max f scl scl clock frequency 0 100 0 400 khz t hd;sta hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 ?0.6 ?s t low low period of the scl clock 4.7 ?1.3 ?s t high high period of the scl clock 4.0 ?0.6 ?s t su;sta setup time for a repeated start condition 4.7 ?0.6 ?s t hd;dat data hold time 0 3.45 0 0.90 s t su;dat data setup time 250 ? 100 [62] ?ns t su;sto setup time for stop condition 4.0 ?0.6 ?s t buf bus free time between a stop and start condition 4.7 ?1.3 ?s t sp pulse width of spikes are suppressed by the input filter ? ?050ns note 62. a fast-mode i 2 c-bus device can be used in a standard mode i 2 c-bus system, but the requirement t su;dat ? 250 ns must then be met. this automatically be the case if the device does not stre tch the low period of the scl signal. if such devi ce does stretch the low period of the scl sig nal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) befor e the scl line is released.
cy8c20xx6a/s document number: 001-54459 rev. *v page 33 of 52 figure 17. spi master mode 0 and 2 figure 18. spi master mode 1 and 3 table 35. spi master ac specifications symbol description conditions min typ max units f sclk sclk clock frequency v dd ? ? 2.4 v v dd < 2.4 v ? ? ? ? 6 3 mhz mhz dc sclk duty cycle ? ? 50 ? % t setup miso to sclk setup time v dd ? 2.4 v v dd < 2.4 v 60 100 ? ? ? ? ns ns t hold sclk to miso hold time ? 40 ? ? ns t out_val sclk to mosi valid time ? ? ? 40 ns t out_h mosi high time ? 40 ? ? ns 1/f sclk t low t high t out_h t hold t setup t out_su msb lsb spi master, modes 0 and 2 sclk (mode 0) sclk (mode 2) miso (input) mosi (output) 1/f sclk t high t low t out_h t hold t setup sclk (mode 1) sclk (mode 3) miso (input) mosi (output) spi master, modes 1 and 3 t out_su msb msb lsb lsb
cy8c20xx6a/s document number: 001-54459 rev. *v page 34 of 52 figure 19. spi slave mode 0 and 2 figure 20. spi slave mode 1 and 3 table 36. spi slave ac specifications symbol description conditions min typ max units f sclk sclk clock frequency ? ? ? 4 mhz t low sclk low time ? 42 ? ? ns t high sclk high time ? 42 ? ? ns t setup mosi to sclk setup time ? 30 ? ? ns t hold sclk to mosi hold time ? 50 ? ? ns t ss_miso ss high to miso valid ? ? ? 153 ns t sclk_miso sclk to miso valid ? ? ? 125 ns t ss_high ss high time ? 50 ? ? ns t ss_clk time from ss low to first sclk ? 2/sclk ? ? ns t clk_ss time from last sclk to ss high ? 2/sclk ? ? ns t clk_ss t ss_high 1/f sclk t low t high t out_h t hold t setup t ss_miso t ss_clk msb lsb spi slave, modes 0 and 2 /ss sclk (mode 0) sclk (mode 2) miso (output) mosi (input) t clk_ss 1/f sclk t high t low t sclk_miso t out_h t hold t setup t ss_clk /ss sclk (mode 1) sclk (mode 3) miso (output) mosi (input) spi slave, modes 1 and 3 t ss_miso msb msb lsb lsb
cy8c20xx6a/s document number: 001-54459 rev. *v page 35 of 52 packaging information this section illustrates the packaging spec ifications for the cy8c20xx6a/s psoc device , along with the thermal impedances for e ach package. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress. com/design/mr10161 . figure 21. 16-pin qfn (no e-pad) (3 3 0.6 mm) lg16a (sawn) p ackage outline, 001-09116 figure 22. 24-pin qfn (4 4 0.55 mm) lq24a 2. 65 2.65 e-pad (sawn) p ackage outline, 001-13937 001-09116 *j 001-13937 *e
cy8c20xx6a/s document number: 001-54459 rev. *v page 36 of 52 figure 23. 32-pin qfn (5 5 0.55 mm) lq32 3.5 3.5 e-pad (sawn) package outline, 001-42168 figure 24. 48-pin ssop (300 mils) o483 package outline, 51-85061 001-42168 *e 51-85061 *f
cy8c20xx6a/s document number: 001-54459 rev. *v page 37 of 52 figure 25. 48-pin qfn (7 7 1.0 mm) lt48a 5.1 5.1 e-pad (sawn) pa ckage outline, 001-13191 figure 26. 48-pin qfn (6 6 0.6 mm) lq48a 4.6 4.6 e-pad (sawn) package outline, 001-57280 important notes for information on the preferred dimensions for mountin g qfn packages, see the following application note at http://www.amkor.com/products/n otes_papers/mlfappnote.pdf . pinned vias for thermal conduction are not required for the low power psoc device. 001-13191 *g 001-57280 *e
cy8c20xx6a/s document number: 001-54459 rev. *v page 38 of 52 thermal impedances capacitance on crystal pins solder reflow specifications ta b l e 3 9 shows the solder reflow temperature limits that must not be exceeded. table 37. thermal impedances per package package typical ? ja [63] typical ? jc 16-pin qfn (no center pad) 33 ? c/w ? 24-pin qfn [64] 21 ? c/w ? 32-pin qfn [64] 20 ? c/w ? 48-pin ssop 69 ? c/w ? 48-pin qfn (6 6 0.6 mm) [64] 25.20 ? c/w 3.04 ? c/w 48-pin qfn (7 7 1.0 mm) [64] 18 ? c/w ? 30-ball wlcsp 54 ? c/w ? table 38. typical package capacitance on crystal pins package package capacitance 32-pin qfn 3.2 pf 48-pin qfn 3.3 pf table 39. solder reflow specifications package maximum peak temperature (t c ) maximum time above t c ? 5 c 16-pin qfn 260 ? c 30 seconds 24-pin qfn 260 ? c 30 seconds 32-pin qfn 260 ? c 30 seconds 48-pin ssop 260 ? c 30 seconds 48-pin qfn (6 6 0.6 mm) 260 ? c 30 seconds 48-pin qfn (7 7 1.0 mm) 260 ? c 30 seconds 30-ball wlcsp 260 ? c 30 seconds notes 63. t j = t a + power ? ja . 64. to achieve the thermal impedance specified for the qfn package, the center thermal pad must be soldered to the pcb ground pl ane.
cy8c20xx6a/s document number: 001-54459 rev. *v page 39 of 52 development tool selection software psoc designer? at the core of the psoc development software suite is psoc designer. utilized by thousands of psoc developers, this robust software has been facilitating psoc designs for over half a decade. psoc designer is available free of charge at http://www.cypress.com . psoc programmer flexible enough to be used on the bench in development, yet suitable for factory progra mming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer. psoc programmer software is compatible with both psoc ice- cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com. development kits all development kits are sold at the cypress online store. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. psoc designer supports the advan ce emulation features also. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66a family cat-5 adapter mini-eval programming board 110 ~ 240 v power supply, euro-plug adapter imagecraft c compiler (registration required) issp cable usb 2.0 cable and blue cat-5 cable 2 cy8c29466a-24pxi 28-pdip chip samples evaluation tools all evaluation tools are sold at the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit enables the user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466a-24pxi pdip psoc device sample 28-pin cy8c27443a-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, and plenty of breadboarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466a-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable cy3280-20x66 universal capsense controller the cy3280-20x66 capsense controller kit is designed for easy prototyping and debug of cy8c20xx6a capsense family designs with pre-defined control circuitry and plug-in hardware. programming hardware and an i2c-to-usb bridge are included for tuning and data acquisition. the kit includes: cy3280-20x66 capsense controller board cy3240-i2usb bridge cy3210 miniprog1 programmer usb 2.0 retractable cable cy3280-20x66 kit cd device programmers all device programmers are purchased from the cypress online store. cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base three programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable
cy8c20xx6a/s document number: 001-54459 rev. *v page 40 of 52 cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production programming environment. note that cy3207issp needs special software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240 v power supply, euro-plug adapter usb 2.0 cable accessories (emulation and programming) third party tools several tools have been specially designed by third-party vend ors to accompany psoc devices dur ing development and production. specific details for each of these tools can be found at http://www.cypress.com under documentation > evaluation boards. build a psoc emulator into your board for details on how to emulate your circuit before going to vo lume production using an on-chip debug (ocd) non-production psoc device, refer application note debugging - build a psoc emulator into your board ? an2323 . table 40. emulation and programming accessories part number pin package flex-pod kit [65] foot kit [66] adapter [67] cy8c20236a-24lkxi 16-pin qfn (no e-pad) cy 3250-20246qfn cy3250-20246qfn-pod see note 64 cy8c20246a-24lkxi 16-pin qfn (no e-pad) cy 3250-20246qfn cy3250-20246qfn-pod see note 67 cy8c20246as-24lkxi 16-pin qfn (no e-pad) not supported cy8c20336a-24lqxi 24-pin qfn cy3250- 20346qfn cy3250-20346qfn-pod see note 64 cy8c20346a-24lqxi 24-pin qfn cy3250-203 46qfn cy3250-20346qfn-pod see note 67 cy8c20346as-24lqxi 24-pin qfn not supported cy8c20396a-24lqxi 24-pin qfn not supported cy8c20436a-24lqxi 32-pin qfn cy3250- 20466qfn cy3250-20466qfn-pod see note 64 cy8c20446a-24lqxi 32-pin qfn cy3250-204 66qfn cy3250-20466qfn-pod see note 67 cy8c20446as-24lqxi 32-pin qfn not supported cy8c20466a-24lqxi 32-pin qfn cy3250-204 66qfn cy3250-20466qfn-pod see note 67 cy8c20466as-24lqxi 32-pin qfn not supported cy8c20496a-24lqxi 32-pin qfn not supported cy8c20536a-24pvxi 48-pin ssop cy325 0-20566 cy3250-20566-pod see note 67 cy8c20546a-24pvxi 48-pin ssop cy325 0-20566 cy3250-20566-pod see note 67 cy8c20566a-24pvxi 48-pin ssop cy325 0-20566 cy3250-20566-pod see note 67 notes 65. flex-pod kit includes a practice flex-pod and a pr actice pcb, in addition to two flex-pods. 66. foot kit includes surface mount feet that can be soldered to the target pcb. 67. programming adapter converts non-dip pa ckage to dip footprint. specific details an d ordering information for each of the ada pters can be found at http://www.emulation.com .
cy8c20xx6a/s document number: 001-54459 rev. *v page 41 of 52 ordering information the following table lists the cy8c20xx6a/s psoc devi ces' key package features and ordering codes. table 41. psoc device key features and ordering information package ordering code flash (bytes) sram (bytes) capsense blocks digital i/o pins analog inputs [68] xres pin usb adc 16-pin (3 3 0.6 mm) qfn (no e-pad) cy8c20236a-24lkxi 8 k 1 k 1 13 13 yes no yes 16-pin (3 3 0.6 mm) qfn (no e-pad) (tape and reel) cy8c20236a-24lkxit 8 k 1 k 1 13 13 yes no yes 16-pin (3 3 0.6 mm) qfn (no e-pad) cy8c20246a-24lkxi 16 k 2 k 1 13 13 yes no yes 16-pin (3 3 0.6 mm) qfn (no e-pad) cy8c20246as-24lkxi 16 k 2 k 1 13 13 yes no yes 16-pin (3 3 0.6 mm) qfn (no e-pad) (tape and reel) cy8c20246a-24lkxit 16 k 2 k 1 13 13 yes no yes 16-pin (3 3 0.6 mm) qfn (no e-pad) (tape and reel) cy8c20246as-24lkxit 16 k 2 k 1 13 13 yes no yes 24-pin (4 4 0.6 mm) qfn cy8c20336a-24lqxi 8 k 1 k 1 20 20 yes no yes 24-pin (4 4 0.6 mm) qfn (tape and reel) cy8c20336a-24lqxit 8 k 1 k 1 20 20 yes no yes 24-pin (4 4 0.6 mm) qfn cy8c20346a-24lqxi 16 k 2 k 1 20 20 yes no yes 24-pin (4 4 0.6 mm) qfn cy8c20346as-24lqxi 16 k 2 k 1 20 20 yes no yes 24-pin (4 4 0.6 mm) qfn (tape and reel) cy8c20346a-24lqxit 16 k 2 k 1 20 20 yes no yes 24-pin (4 4 0.6 mm) qfn (tape and reel) cy8c20346as-24lqxit 16 k 2 k 1 20 20 yes no yes 24-pin (4 4 0.6 mm) qfn cy8c20396a-24lqxi 16 k 2 k 1 19 19 yes yes yes 24-pin (4 4 0.6 mm) qfn (tape and reel) cy8c20396a-24lqxit 16 k 2 k 1 19 19 yes yes yes 32-pin (5 5 0.6 mm) qfn cy8c20436a-24lqxi 8 k 1 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn (tape and reel) cy8c20436a-24lqxit 8 k 1 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn cy8c20446a-24lqxi 16 k 2 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn cy8c20446as-24lqxi 16 k 2 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn (tape and reel) cy8c20446a-24lqxit 16 k 2 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn (tape and reel) cy8c20446as-24lqxit 16 k 2 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn cy8c20466a-24lqxi 32 k 2 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn cy8c20466as-24lqxi 32 k 2 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn (tape and reel) cy8c20466a-24lqxit 32 k 2 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn (tape and reel) cy8c20466as-24lqxit 32 k 2 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn cy8c20496a-24lqxi 16 k 2 k 1 25 25 yes yes yes 32-pin (5 5 0.6 mm) qfn (tape and reel) cy8c20496a-24lqxit 16 k 2 k 1 25 25 yes yes yes
cy8c20xx6a/s document number: 001-54459 rev. *v page 42 of 52 48-pin ssop [69] cy8c20536a-24pvxi [69] 8 k 1 k 1 34 34 yes no yes 48-pin ssop (tape and reel) [69] cy8c20536a-24pvxit [69] 8 k 1 k 1 34 34 yes no yes 48-pin ssop [69] cy8c20546a-24pvxi [69] 16 k 2 k 1 34 34 yes no yes 48-pin ssop (tape and reel) [69] cy8c20546a-24pvxit [69] 16 k 2 k 1 34 34 yes no yes 48-pin ssop [69] cy8c20566a-24pvxi [69] 32 k 2 k 1 34 34 yes no yes 48-pin ssop (tape and reel) [69] cy8c20566a-24pvxit [69] 32 k 2 k 1 34 34 yes no yes 48-pin (6 6 0.6 mm) qfn cy8c20636a-24lqxi 8 k 1 k 1 36 36 yes no yes 48-pin (6 6 0.6 mm) qfn (tape and reel) cy8c20636a-24lqxit 8 k 1 k 1 36 36 yes no yes 48-pin (7 7 1.0 mm) qfn [69] cy8c20636a-24ltxi [69] 8 k 1 k 1 36 36 yes no yes 48-pin (7 7 1.0 mm) qfn (tape and reel) [69] cy8c20636a-24ltxit [69] 8 k 1 k 1 36 36 yes no yes 48-pin (6 6 0.6 mm) qfn CY8C20646A-24LQXI 16 k 2 k 1 36 36 yes yes yes 48-pin (6 6 0.6 mm) qfn (tape and reel) CY8C20646A-24LQXIt 16 k 2 k 1 36 36 yes yes yes 48-pin (7 7 1.0 mm) qfn [69] cy8c20646a-24ltxi [69] 16 k 2 k 1 36 36 yes yes yes 48-pin (7 7 1.0 mm) qfn (tape and reel) [69] cy8c20646a-24ltxit [69] 16 k 2 k 1 36 36 yes yes yes 48-pin (6 6 0.6 mm) qfn cy8c20666a-24lqxi 32 k 2 k 1 36 36 yes yes yes 48-pin (6 6 0.6 mm) qfn (tape and reel) cy8c20666a-24lqxit 32 k 2 k 1 36 36 yes yes yes 48-pin (7 7 1.0 mm) qfn [69] cy8c20666a-24ltxi [69] 32 k 2 k 1 36 36 yes yes yes 48-pin (7 7 1.0 mm) qfn [69] cy8c20666as-24ltxi [69] 32 k 2 k 1 36 36 yes yes yes 48-pin (7 7 1.0 mm) qfn (tape and reel) [69] cy8c20666a-24ltxit [69] 32 k 2 k 1 36 36 yes yes yes 48-pin (7 7 1.0 mm) qfn (tape and reel) [69] cy8c20666as-24ltxit [69] 32 k 2 k 1 36 36 yes yes yes 48-pin (7 7 1.0 mm) qfn (ocd) [68] cy8c20066a-24ltxi [68] 32 k 2 k 1 36 36 yes yes yes 30-ball wlcsp cy8c20746a-24fdxc 16 k 1 k 1 27 27 yes no yes 30-ball wlcsp (tape and reel) cy8c20746a-24fdxct 16 k 1 k 1 27 27 yes no yes 30-ball wlcsp cy8c20766a-24fdxc 32 k 2 k 1 27 27 yes no yes 30-ball wlcsp (tape and reel) cy8c20766a-24fdxct 32 k 2 k 1 27 27 yes no yes 24-pin (4 4 0.6 mm) qfn cy8c20336an-24lqxi 8 k 1 k 1 20 20 yes no no 24-pin (4 4 0.6 mm) qfn (tape and reel) cy8c20336an-24lqxit 8 k 1 k 1 20 20 yes no no 32-pin (5 5 0.6 mm) qfn cy8c20436an-24lqxi 8 k 1 k 1 28 28 yes no no 32-pin (5 5 0.6 mm) qfn (tape and reel) cy8c20436an-24lqxit 8 k 1 k 1 28 28 yes no no 48-pin (7 7 1.0 mm) qfn [69] cy8c20636an-24ltxi [69] 8 k 1 k 1 36 36 yes no no 48-pin (7 7 1.0 mm) qfn (tape and reel) [69] cy8c20636an-24ltxit [69] 8 k 1 k 1 36 36 yes no no table 41. psoc device key features and ordering information (continued) package ordering code flash (bytes) sram (bytes) capsense blocks digital i/o pins analog inputs [68] xres pin usb adc
cy8c20xx6a/s document number: 001-54459 rev. *v page 43 of 52 ordering code definitions 16-pin (3 3 0.6 mm) qfn (no e-pad) cy8c20246as-24lkxi 16 k 2 k 1 13 13 yes no yes 16-pin (3 3 0.6 mm) qfn (no e-pad, tape and reel) cy8c20246as-24lkxit 16 k 2 k 1 13 13 yes no yes 24-pin (4 4 0.6 mm) qfn cy8c20346as-24lqxi 16 k 2 k 1 20 20 yes no yes 24-pin (4 4 0.6 mm) qfn (tape and reel) cy8c20346as-24lqxit 16 k 2 k 1 20 20 yes no yes 32-pin (5 5 0.6 mm) qfn cy8c20446as-24lqxi 16 k 2 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn (tape and reel) cy8c20446as-24lqxit 16 k 2 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn cy8c20466as-24lqxi 32 k 2 k 1 28 28 yes no yes 32-pin (5 5 0.6 mm) qfn (tape and reel) cy8c20466as-24lqxit 32 k 2 k 1 28 28 yes no yes 48-pin (6 6 0.6 mm) qfn cy8c20666as-24lqxi 32 k 2 k 1 36 36 yes yes yes 48-pin (6 6 0.6 mm) qfn (tape and reel) cy8c20666as-24lqxit 32 k 2 k 1 36 36 yes yes yes 48-pin (7 7 1.0 mm) qfn [69] cy8c20666as-24ltxi [69] 32 k 2 k 1 36 36 yes yes yes 48-pin (7 7 1.0 mm) qfn (tape and reel) [69] cy8c20666as-24ltxit [69] 32 k 2 k 1 36 36 yes yes yes 48-pin (6 6 0.6 mm) qfn cy8c20646as-24lqxi 16 k 2 k 1 36 36 yes yes yes 48-pin (6 6 0.6 mm) qfn (tape and reel) cy8c20646as-24lqxit 16 k 2 k 1 36 36 yes yes yes 48-pin (7 7 1.0 mm) qfn [69] cy8c20646as-24ltxi [69] 16 k 2 k 1 36 36 yes yes yes 48-pin (7 7 1.0 mm) qfn (tape and reel) [69] cy8c20646as-24ltxit [69] 16 k 2 k 1 36 36 yes yes yes table 41. psoc device key features and ordering information (continued) package ordering code flash (bytes) sram (bytes) capsense blocks digital i/o pins analog inputs [68] xres pin usb adc tape and reel temperature range: x = c or i c = commercial; i = industrial pb-free package type: xx = lk or lq or pv or lt or fd lk = 16-pin qfn (no e-pad) lq = 24-pin qfn, 32-pin qfn, 48-pin (6 6 0.6 mm) qfn pv = 48-pin ssop lt = 48-pin (7 7 1.0 mm) qfn fd = 30-ball wlcsp speed grade: 24 mhz part number family code technology code: c = cmos marketing code: 8 = psoc company id: cy = cypress c 20 xx6ax - 24 x xx t cy 8 x notes 68. dual-function digital i/o pins also connect to the common analog mux. 69. not recommended for new designs.
cy8c20xx6a/s document number: 001-54459 rev. *v page 44 of 52 acronyms reference documents technical reference manual for cy8c20xx6 devices in-system serial programming (issp) protocol for 20xx6 ( an2026c ) host sourced serial programming for 20xx6 devices (an59389 ) document conventions units of measure table 42. acronyms used in this document acronym description ac alternating current adc analog-to-digital converter api application programming interface cmos complementary metal oxide semiconductor cpu central processing unit dac digital-to-analog converter dc direct current eop end of packet fsr full scale range gpio general purpose input/output gui graphical user interface i 2 c inter-integrated circuit ice in-circuit emulator idac digital analog converter current ilo internal low speed oscillator imo internal main oscillator i/o input/output issp in-system serial programming lcd liquid crystal display ldo low dropout (regulator) lsb least-significant bit lvd low voltage detect mcu micro-controller unit mips mega instructions per second miso master in slave out mosi master out slave in msb most-significant bit ocd on-chip debugger por power on reset ppor precision power on reset psrr power supply rejection ratio pwrsys power system psoc ? programmable system-on-chip slimo slow internal main oscillator sram static random access memory snr signal to noise ratio qfn quad flat no-lead scl serial i2c clock sda serial i2c data sdata serial issp data spi serial peripheral interface ss slave select ssop shrink small outline package tc test controller usb universal serial bus usb d+ usb data+ usb d? usb data? wlcsp wafer level chip scale package xtal crystal table 43. units of measure symbol unit of measure c degree celsius db decibels ff femtofarad g gram hz hertz kb 1024 bytes kbit 1024 bits khz kilohertz ksps kilo samples per second k ? kilohm mhz megahertz m ? megaohm ? a microampere ? f microfarad ? h microhenry ? s microsecond ? w microwatt ma milliampere ms millisecond mv millivolt na nanoampere nf nanofarad ns nanosecond nv nanovolt w ohm pa picoampere pf picofarad pp peak-to-peak ppm parts per million ps picosecond sps samples per second s sigma: one standard deviation v volt w watt
cy8c20xx6a/s document number: 001-54459 rev. *v page 45 of 52 numeric naming hexadecimal numbers are represented with all letters in uppercas e with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pr efix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h?, ?b?, or 0x are decimal. glossary crosspoint connection connection between any gpio combination via analog multiplexer bus. differential non-linearity ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one lsb apart. differential non-linearity is a measure of the worst case deviation from the ideal 1 lsb step. hold time hold time is the time following a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct. i 2 c it is a serial multi-master bus used to connect low speed peripherals to mcu. integral nonlinearity it is a term describing the maximum deviation between the idea l output of a dac/adc and the actual output level. latch-up current current at which the latch-up test is conducted according to jesd78 standard (at 125 degree celsius) power supply rejection ratio (psrr) the psrr is defined as th e ratio of the change in supply voltage to the corresponding change in output voltage of the device. scan the conversion of all sensor capacitances to digital values. setup time period r equired to prepare a device, machine, proc ess, or system for it to be ready to function. signal-to-noise ratio the ratio between a capacitive finger signal and system noise. spi serial peripheral interface is a synchronous serial data link standard.
cy8c20xx6a/s document number: 001-54459 rev. *v page 46 of 52 errata this section describes the errata for the psoc ? cy8c20x36a/46a/66a/96a/46as/66as/36h/46h families. details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. contact your local cypress sale s repre- sentative if you have questions. qualification status product status: production released. errata summary the following errata items apply to cy8c20 x36a/46a/66a/96a/46as/66as/36h/46h families. 1. wakeup from sleep may intermittently fail problem definition when the device is put to sleep in standby or i2c_usb mode an d the bandgap circuit is refreshed less frequently than every 8 ms (default), the device may not come out of sleep when a sleep-ending input is received. parameters affected none trigger condition(s) by default, when the device is in the standby or i2c_usb slee p modes, the bandgap circuit is powered-up approximately every 8 ms to facilitate detection of por or lvd events. this interv al can be lengthened or the periodic power-up disabled to reduce sl eep current by setting the alt_buzz bits in the slp_cfg2 register or the disable buzz bit in the osc_cr0 register respectively. if the bandgap circuit refresh interval is set longer than the default 8 ms, the device may fail to wakeup from sleep and enter a locked up state that can only be recovere d by watchdog reset, xres, or por. scope of impact the trigger conditions outlined above may cause the device to never wakeup. workaround prior to entering standby or i2c_usb sleep modes, do not lengthen or disable the bandg ap refresh interval by manipulating the alt_buzz bits in the slp_cfg2 register or the disable buzz bit in the osc_cr0 register respectively. fix status this issue will not be corrected in the next silicon revision. 2. i 2 c errors problem definition the i 2 c block exhibits occasional data and bus corruption errors when the i 2 c master initiates transactions while the device is transitioning in to or out of sleep mode. parameters affected affects reliability of i 2 c communication to device, and between i 2 c master and third party i 2 c slaves. trigger condition(s) triggered by transitions into and out of the device?s sleep mode. scope of impact data errors result in incorrect data reported to the i 2 c master, or incorrect data received from the master by the device. bus corruption errors can corrupt data in transactions between the i 2 c master and third party i 2 c slaves. workaround firmware workarounds are available in firmware. genera lly the workaround consists of disconnecting the i 2 c block from the bus prior to going to sleep modes. i 2 c transactions during sleep are supported by a protoc ol in which the master wakes the device prior to the i 2 c transaction. fix status to be fixed in future silicon.
cy8c20xx6a/s document number: 001-54459 rev. *v page 47 of 52 changes none 3. doubletimer0 isr problem definition when programmable timer 0 is used in ?one-shot? mode by setting bit 1 of register 0,b0h (pt0_c fg), and the timer interrupt is used to wake the device from sleep, the inte rrupt service routine (isr) may be executed twice. parameters affected no datasheet parameters are affected. trigger condition(s) triggered by enabling one-shot mode in the timer, and using the timer to wake from sleep mode. scope of impact the isr may be executed twice. workaround in the isr, firmware should clear the one-shot bit with a statement such as ? and reg[b0h], fdh ? fix status will not be fixed changes none 4. missed gpio interrupt problem definition when in sleep mode, if a gpio interrupt happens simultaneously wi th a timer0 or sleep timer interrupt, the gpio interrupt may be missed, and the corresponding gpio isr not run. parameters affected no datasheet parameters are affected. trigger condition(s) triggered by enabling sleep mode, then having gpio interrupt o ccur simultaneously with a timer 0 or sleep timer interrupt. scope of impact the gpio interrupt service routine will not be run. workaround the system should be architected such that a missed gpio interrupt may be detected. for example, if a gpio is used to wake the system to perform some function, the system should detect if the function is not performed, and re-issue the gpio interrupt . alternatively, if a gpio interrupt is required to wake the system, then firmware should disable the sleep timer and timer0. alternatively, the isr?s for sleep timer and timer0 should manua lly check the state of the gpio to determine if the host system has attempted to gener ate a gpio interrupt. fix status will not be fixed changes none
cy8c20xx6a/s document number: 001-54459 rev. *v page 48 of 52 5. missed interrupt during transition to sleep problem definition if an interrupt is posted a short time (within 2.5 cpu cycles) before firmware commands the devic e to sleep, the interrupt will be missed. parameters affected no datasheet parameters are affected. trigger condition(s) triggered by enabling sleep mode just prior to an interrupt. scope of impact the relevant interrupt serv ice routine will not be run. workaround none. fix status will not be fixed changes none 6. wakeup from sleep with analog interrupt problem definition device wakes up from sleep when an analog interrupt is trigger parameters affected no datasheet parameters are affected. trigger condition(s) triggered by enabling analog interrupt during sleep mode when device operating temperature is 50 c or above scope of impact device unexpectedly wakes up from sleep workaround disable the analog interrupt before entering sleep and turn it back on upon wakeup. fix status will not be fixed changes none
cy8c20xx6a/s document number: 001-54459 rev. *v page 49 of 52 document history page document title: cy8c20xx6a/s, 1.8 v programmable capsense ? controller with smartsense ? auto-tuning 1?33 buttons, 0?6 sliders document number: 001-54459 revision ecn orig. of change submission date description of change ** 2737924 snv 07/14/09 new silicon and document *a 2764528 matt 09/16/2009 updated ac chip level specifications updated adc user module electrical specifications table added note 5. added sr power_up parameter. updated ordering information. updated capacitance on crystal pins *b 2803229 vzd 11/10/09 added ?contents? on page 4. added note 6 on page 20. edited features section to include reference to incremental adc. *c 2846083 dst / kejo 01/12/2010 updated ?ac programming specifications? on page 31 per cdt 56531. updated idd typical values in ?dc chip-level specifications? on page 21. added 30-pin wlcsp pin and package details. added contents on page 2. *d 2935141 kejo / isw / sshh 03/05/2010 updated ?features? on page 1. added ?smartsense? on page 5. updated ?psoc ? functional overview? on page 5. removed snr statement regarding on pa ge 4 (analog multiplexer section). updated ?? on page 8 with the i2c enhanced slave interface point. removed references to ?system level? in ?designing with psoc designer? on page 9. changed tc clk and tc data to issp clk and issp data respectively in all the pinouts. modified notes in pinouts. updated 30-ball pin diagram. removed imo frequency trim options diagram in ?electrical specifications? on page 20. updated and formatted values in dc and ac specifications. updated ordering information table. updated 48-pin ssop package diagram. added 30-ball wlcsp package spec 001-50669. removed ac analog mux bus specifications section. added spi master and slave mode diagrams. modified definition for timing for fast/standard mode on the i2c bus on page 28 . updated ?thermal impedances? on page 38. combined development tools with ?development tool selection? on page 39. removed references to ?system level?. updated ?evaluation tools? on page 39. added ?ordering code definitions? on page 43. updated ?acronyms? on page 44. added glossary and ?reference documents? on page 44. changed datasheet status from preliminary to final *e 3043291 saac 09/30/10 change: added the line ?supports smar tsense? in the ?low power capsense ? block? bullet in the features section. impact: helps to know that this part has the feature of auto tuning. change: replaced pod mpns. areas affected: foot kit column of table 37. change: template and styles update. areas affected: entire datasheet. impact: datasheet adheres to cypress standards. *f 3071632 jpx 10/26/10 in table 36 on page 34 , modified t low and t high min values to 42. updated t ss_high min value to 50; removed max value.
cy8c20xx6a/s document number: 001-54459 rev. *v page 50 of 52 *g 3247491 tto / jpm / arvm / bvi 06/16/11 add 4 new parameters to table 14 on page 22 , and 2 new parameters to table 15 on page 23 . changed typ values for the following parameters: i dd24, i dd12, i dd6, v oslpc. added footnote # 40 and referred it to pin numbers 1, 14, 15, 42, and 43 under table 10 on page 19 . added footnote # 43 and referred it to parameter v ioz under table 11 on page 20 . added ?t jit_imo ? parameter to table 27 on page 28 . included footnote # 59 and added reference to t jit_imo specification under table 27 on page 28 . updated solder reflow specifications on page 38 as per specs 25-00090 and 25-00103. i sb0 max value changed from 0.5 a to 1.1 a in table 13 on page 21 . added table 26 on page 27. updated part numbers for ?smartsens e_emc? enabled capsense controller. *h 3367332 btk / sshh / jpm / tto / vmad 09/09/11 added parameter ?t os ? to table 27 on page 28 . added parameter ?i sbi2c ? to table 13 on page 21 . added table 24 on page 27. added table 25 on page 27. replaced text ?port 2 or 3 pins? with ?port 2 or 3 or 4 pins? in table 14 , ta b l e 1 5 , table 16 , and table 28 . *i 3371807 matt 09/30/2011 updated packaging information (updated the next revision package outline for figure 21 , figure 24 and included a new package outline figure 26 ). updated ordering information (added new part numbers cy8c20636a-24lqxi, cy8c20636a-24lqxit, CY8C20646A-24LQXI, CY8C20646A-24LQXIt, cy8c20666a-24lqxi, cy8c20666a-24lqxit, cy8c20666as-24lqxi, cy8c20666as -24lqxit, cy8c20646as-24lqxi and cy8c20646as-24lqxit). updated in new template. *j 3401666 matt 10/11/2011 no technical updates. *k 3414479 kpol 10/19/2011 removed clo ck stretching feature on page 1. removed i 2 c enhanced slave interface point from additional system resources . *l 3452591 bvi / udyg 12/01/2011 changed document title. updated dc chip-level specifications table. updated solder reflow specifications section. updated getting started and designing with psoc designer sections. included development tools section. updated software under development tool selection section. *m 3473330 anba 12/22/2011 updated dc chip-level specifications under electrical specifications (updated maximum value of i sb0 parameter from 1.1 a to 1.05 a). *n 3587003 dst 04/16/2012 added note for wlcsp package on page 1. added sensing inputs to pin table captions. updated conditions for dc reference buffer specifications . updated t jit_imo description in ac chip-level specifications . added note for t vddwait , t vddxres , t acq , and t xresini specs. removed wlcsp package outline. *o 3638569 bvi 06/06/2012 updated f sclk parameter in the table 36, ?spi slave ac specifications,? on page 34. changed t out_high to t out_h in table 35, ?spi master ac specifications,? on page 33. updated package diagram 001-57280 to *c revision. document history page (continued) document title: cy8c20xx6a/s, 1.8 v programmable capsense ? controller with smartsense ? auto-tuning 1?33 buttons, 0?6 sliders document number: 001-54459 revision ecn orig. of change submission date description of change
cy8c20xx6a/s document number: 001-54459 rev. *v page 51 of 52 *p 3774062 ubu 10/11/2012 updated min value of parameter f 32k1 (from 19 to 15) in the table 27, ?ac chip-level specifications,? on page 28. updated packaging information for 001-09116 (*f to *g), 001-13937 (*d to *e), 51-85061 (*e to *f), 001-13191 (*f to *g), and 001-57280 (*c to *d). *q 3807186 pks 15/11/2012 no content update; appended to eros document. *r 3836626 srli 01/03/2013 updated document title to read as ?cy8c20xx6a/s, 1.8 v programmable capsense ? controller with smartsense? auto-tuning 1?33 buttons, 0?6 sliders?. updated features . updated psoc ? functional overview : replaced ?cy8c20x36a/46a/66a/96a/ 46as/66as? with ?cy8c20xx6a/s?. updated getting started : replaced ?cy8c20x36a/46a/66a/96a/ 46as/66as? with ?cy8c20xx6a/s?. updated pinouts : updated 16-pin qfn (10 sensing inputs)[3, 4] : replaced ?12 sensing inputs? with ?10 sensing inputs? in heading, added note 3 only. updated 24-pin qfn (17 sensing inputs) [7] : replaced ?12 sensing inputs? with ?17 sensing inputs? in heading, added note 7 only. updated 24-pin qfn (15 sensing inputs (with usb)) [11] : replaced ?18 sensing inputs? with ?15 sensing inputs? in heading, added note 11 only. updated 30-ball wlcsp (24 sensing inputs) [15] : replaced ?26 sensing inputs? with ?24 sensing inputs? in heading, added note 15 only. updated 32-pin qfn (25 sensing inputs) [18] : replaced ?27 sensing inputs? with ?25 sensing inputs? in heading, added note 18 only. updated 32-pin qfn (22 sensing inputs (with usb)) [22] : replaced ?24 sensing inputs? with ?22 sensing inputs? in heading, added note 22 only. updated 48-pin ssop (31 sensing inputs) [26] : replaced ?33 sensing inputs? with ?31 sensing inputs? in heading, added note 26 only. updated 48-pin qfn (33 sensing inputs) [29] : replaced ?35 sensing inputs? with ?33 sensing inputs? in heading, added note 29 only. updated 48-pin qfn (33 sensing inputs (with usb)) [33] : replaced ?35 sensing inputs? with ?33 sensing inputs? in heading, added note 33 only. updated 48-pin qfn (ocd) (33 sensing inputs) [37] : added ?33 sensing inputs? in heading, added note 37 only. updated packaging information : spec 001-42168 ? changed revision from *d to *e. spec 001-57280 ? changed revision from *d to *e. *s 3997568 bvi 05/11/2013 added errata . *t 4044148 bvi 06/28/2013 added errata footnotes. updated packaging information : spec 001-09116 ? changed revision from *g to *h. updated in new template. *u 4185313 bvi 11/07/2013 updated features . updated packaging information : spec 001-09116 ? changed revision from *h to *i. *v 4622119 sshh 01/13/2015 added more information section. document history page (continued) document title: cy8c20xx6a/s, 1.8 v programmable capsense ? controller with smartsense ? auto-tuning 1?33 buttons, 0?6 sliders document number: 001-54459 revision ecn orig. of change submission date description of change
document number: 001-54459 rev. *v revised january 13, 2015 page 52 of 52 psoc designer? is a trademark and psoc ? and capsense ? are registered trademarks of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c20xx6a/s ? cypress semiconductor corporation, 2009-2015. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support
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